| 2000 | Self-Testing of Linear Segments in User-Programmed FPGAs. | Pawel Tomaszewicz |
| 2000 | Balancing Logic Utilization and Area Efficiency in FPGAs. | Russell Tessier, Heather Giza |
| 2000 | A Compiler Directed Approach to Hiding Configuration Latency in Chameleon Processors. | Xinan Tang, Manning Aalsma, Raymond Jou |
| 2000 | FPL Curriculum at Tallinn Technical University. | Kalle Tammeme, T. Evartson |
| 2000 | Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware. | Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu Amano |
| 2000 | On Availability of Bit-Narrow Operations in General-Purpose Applications. | Darko Stefanovic, Margaret Martonosi |
| 2000 | Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs. | Valery Sklyarov |
| 2000 | Multitasking on FPGA Coprocessors. | Harald Simmler, L. Levinson, Reinhard Mnner |
| 2000 | Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling. | Christian Siemers |
| 2000 | A Self-Reconfigurable Gate Array Architecture. | Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro Mei, Viktor K. Prasanna |
| 2000 | An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture. | Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada |
| 2000 | Toward Uniform Approach to Design of Evolvable Hardware Based Systems. | Luks Sekanina, Azeddien M. Sllame |
| 2000 | Formal Verification of a Reconfigurable Microprocessor. | Sergej Sawitzki, Jens Schnherr, Rainer G. Spallek, Bernd Straube |
| 2000 | Verification of Dynamically Reconfigurable Logic. | David Robinson, Patrick Lysaght |
| 2000 | A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs. | Tero Rissa, Jarkko Niittylahti |
| 2000 | Software Radio Reconfigurable Hardware System (SHaRe). | Xavier Revs, Antoni Gelonch, Ferran Casadevall, Jos L. Garca |
| 2000 | A Specific Test Methodology for Symmetric SRAM-Based FPGAs. | Michel Renovell |
| 2000 | Field Programmable Communication Emulation and Optimization for Embedded System Design. | Frank-Michael Renner, Jrgen Becker, Manfred Glesner |
| 2000 | A Parallel Pipelined SAT Solver for FPGAs. | Mark Redekopp, Andreas Dandalis |
| 2000 | Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. | Javier Ramrez, Antonio Garca, Pedro G. Fernndez, Luis Parrilla, Antonio Lloris-Ruz |
| 2000 | The Modular Architecture of SYNTHUP, FPFA Based PCI Board for Real-Time Sound Synthesis and Digital Signal Processing. | Jean-Michel Raczinski, Stphane Sladek |
| 2000 | Silicon Platforms for the Next Generation Wireless Systems - What Role Does Reconfigurable Hardware Play? | Jan M. Rabaey |
| 2000 | Optimum Functional Decomposition for LUT-Based FPGA Synthesis. | Jian Qiao, Makoto Ikeda, Kunihiro Asada |
| 2000 | Security Upgrade of Existing ISDN Devices by Using Reconfigurable Logic. | Hagen Ploog, Mathias Schmalisch, Dirk Timmermann |
| 2000 | Wireless Base Station Design Using a Reconfigurable Communications Processor. | Chris Phillips |