| 2020 | Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs. | Kahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton |
| 2020 | Using Novel Configuration Techniques for Accelerated FPGA Aging. | Tanner Gaskin, Hayden Cook, Wesley Stirk, Robert Lucas, Jeffrey Goeders, Brad L. Hutchings |
| 2020 | On the Feasibility of TERO-Based True Random Number Generator on Xilinx FPGAs. | Naoki Fujieda |
| 2020 | A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs. | Richard Dorrance, Andrey Belogolovy, Hechen Wang, Xue Zhang |
| 2020 | Agile Autotuning of a Transprecision Tensor Accelerator Overlay for TVM Compiler Stack. | Dionysios Diamantopoulos, Burkhard Ringlein, Mitra Purandare, Gagandeep Singh, Christoph Hagleitner |
| 2020 | Design for ReConfigurability: An Electronic System Level Methodology to Exploit Reconfigurable Platforms. | Gabriella D'Andrea, Luigi Pomante |
| 2020 | Characterizing Latency Overheads in the Deployment of FPGA Accelerators. | Ryan A. Cooke, Suhaib A. Fahmy |
| 2020 | Side Channel Resistance at a Cost: A Comparison of ARX-Based Authenticated Encryption. | Flora Coleman, Behnaz Rezvani, Sachin Sachin, William Diehl |
| 2020 | Weighing Up the New Kid on the Block: Impressions of using Vitis for HPC Software Development. | Nick Brown |
| 2020 | Compact and Programmable yet High-Performance SoC Architecture for Cryptographic Pairings. | Milad Bahadori, Kimmo Jrvinen |
| 2020 | High-Speed Chromatic Dispersion Compensation Filtering in FPGAs for Coherent Optical Communication. | Cheolyong Bae, Oscar Gustafsson |
| 2020 | LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs. | Farah Abid, Darshana Jayasinghe, Sompasong Somsavaddy, Sri Parameswaran |
| 2020 | Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework. | Nuno Paulino, Joo Canas Ferreira, Joo Bispo, Joo M. P. Cardoso |
| 2019 | A Data-Center FPGA Acceleration Platform for Convolutional Neural Networks. | Xiaoyu Yu, Jianlin Gao, Yuwei Wang, Jie Miao, Ephrem Wu, Heng Zhang, Yu Meng, Bo Zhang, Biao Min, Dewei Chen |
| 2019 | Blocks: Redesigning Coarse Grained Reconfigurable Architectures for Energy Efficiency. | Mark Wijtvliet, Jos Huisken, Luc Waeijen, Henk Corporaal |
| 2019 | Hybrid Dot-Product Calculation for Convolutional Neural Networks in FPGA. | Mrio P. Vstias, Rui Policarpo Duarte, Jos T. de Sousa, Horcio C. Neto |
| 2019 | Automatic Compiler Based FPGA Accelerator for CNN Training. | Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo |
| 2019 | The FOS (FPGA Operating System) Demo. | Anuj Vaishnav, Khoa Dang Pham, Kristiyan Manev, Dirk Koch |
| 2019 | Evaluating the Hardware Cost of the Posit Number System. | Yohann Uguen, Luc Forget, Florent de Dinechin |
| 2019 | Accelerating Physics Engine Components with Embedded FPGAs. | Petros Toupas, Andreas Brokalakis, Ioannis Papaefstathiou |
| 2019 | FPGA-Based Simulated Bifurcation Machine. | Kosuke Tatsumura, Alexander Dixon, Hayato Goto |
| 2019 | Spiking Row-by-Row FPGA Multi-Kernel and Multi-Layer Convolution Processor. | Ricardo Tapiador-Morales, Antonio Rios-Navarro, Juan Pedro Dominguez-Morales, Daniel Gutierrez-Galan, Alejandro Linares-Barranco |
| 2019 | OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs. | Xifan Tang, Edouard Giacomin, Aurlien Alacchi, Baudouin Chauviere, Pierre-Emmanuel Gaillardon |
| 2019 | Bent Routing Pattern for FPGA. | Xibo Sun, Hao Zhou, Lingli Wang |
| 2019 | NARMADA: Near-Memory Horizontal Diffusion Accelerator for Scalable Stencil Computations. | Gagandeep Singh, Dionysios Diamantopoulos, Christoph Hagleitner, Sander Stuijk, Henk Corporaal |