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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2019Demonstration of a Multimode SoC FPGA-Based Acoustic Camera.Bruno da Silva, Laurent Segers, An Braeken, Abdellah Touhafi
2019High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing.Roberto Sierra, Filippo Mangani, Carlos Carreras, Gabriel Caffarena
2019An FPGA Implementation of Real-Time Object Detection with a Thermal Camera.Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Hiroki Nakahara
2019Scaling the Cascades: Interconnect-Aware FPGA Implementation of Machine Learning Problems.Ananda Samajdar, Tushar Garg, Tushar Krishna, Nachiket Kapre
2019Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack.Mario Ruiz, David Sidler, Gustavo Sutter, Gustavo Alonso, Sergio Lpez-Buedo
2019System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration.Burkhard Ringlein, Franois Abel, Alexander Ditter, Beat Weiss, Christoph Hagleitner, Dietmar Fey
2019A Low-Latency Multi-Version Key-Value Store Using B-Tree on an FPGA-CPU Platform.Yuchen Ren, Zhijian Liao, Xiaozhong Shi, Jinyu Xie, Yunhui Qiu, Hankun Lv, Wenbo Yin, Lingli Wang, Bowei Yu, Hua Chen, Xianjun He
2019A Flexible Design Automation Tool for Accelerating Quantized Spectral CNNs.Rachit Rajat, Hanqing Zeng, Viktor K. Prasanna
2019Characterizing Power Distribution Attacks in Multi-User FPGA Environments.George Provelengios, Daniel E. Holcomb, Russell Tessier
2019The CEDARtools Platform - Massive External Memory with High Bandwidth and Low Latency Under Fine-Granular Random Access Patterns.Thomas Preuer, Alexander Weiss
2019Reducing Dynamic Power in Streaming CNN Hardware Accelerators by Exploiting Computational Redundancies.Duvindu Piyasena, Rukshan Wickramasinghe, Debdeep Paul, Siew-Kei Lam, Meiqing Wu
2019Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow.Johan Peltenburg, Jeroen van Straten, Lars Wijtemans, Lars van Leeuwen, Zaid Al-Ars, H. Peter Hofstee
2019A Highly-Portable True Random Number Generator Based on Coherent Sampling.Adriaan Peetermans, Vladimir Rozic, Ingrid Verbauwhede
2019A Self-Calibrating True Random Number Generator.Adriaan Peetermans, Milos Grujic, Vladimir Rozic, Ingrid Verbauwhede
2019Runtime-Programmable Pipelines for Model Checkers on FPGAs.Mrunal Patel, Shenghsun Cho, Michael Ferdman, Peter A. Milder
2019Accelerating the Merge Phase of Sort-Merge Join.Philippos Papaphilippou, Holger Pirk, Wayne Luk
2019Low-Level Loop Analysis and Pipelining of Applications Mapped to Xilinx FPGAs.Hossein Omidian, Guy G. F. Lemieux
2019ZytleBot: FPGA Integrated Development Platform for ROS Based Autonomous Mobile Robot.Yasuhiro Nitta, Sou Tamura, Hideki Takase
2019Finding a Needle in the Haystack of Hardened Interconnect Patterns.Stefan Nikolic, Grace Zgheib, Paolo Ienne
2019Quantifying the Benefits of Dynamic Partial Reconfiguration for Embedded Vision Applications.Marie Nguyen, Robert Tamburo, Srinivasa G. Narasimhan, James C. Hoe
2019Tinsel: A Manythread Overlay for FPGA Clusters.Matthew Naylor, Simon W. Moore, David B. Thomas
2019FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network.Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato
2019Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey.Seyedeh Sharareh Mirzargar, Mirjana Stojilovic
2019Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device.Seungwon Min, Sitao Huang, Mohamed El-Hadedy, Jinjun Xiong, Deming Chen, Wen-Mei Hwu
2019Analysis of Performance Variation in 16nm FinFET FPGA Devices.Konstantinos Maragos, Endri Taka, George Lentaris, Ioannis Stratakos, Dimitrios Soudris
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