Field Programmable Logic and Applications

FPL

CORE rank

CORE rank (raw)

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Best Computer Systems Engineering conferences

Papers per year

1994182 peak2025

Most published authors

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

Year	Title	Authors
2014	Exploring architecture parameters for dual-output LUT based FPGAs.	Zhenghong Jiang, Colin Yu Lin, Liqun Yang, Fei Wang, Haigang Yang
2014	A survey of open source processors for FPGAs.	Rui Jia, Colin Yu Lin, Zhenhong Guo, Rui Chen, Fei Wang, Tongqiang Gao, Haigang Yang
2014	Radix-4 and radix-8 booth encoded interleaved modular multipliers over general Fp.	Khalid Javeed, Xiaojun Wang
2014	TransPar: Transformation based dynamic Parallelism for low power CGRAs.	Syed M. A. H. Jafri, Guilermo Serrano, Masoud Daneshtalab, Naeem Abbas, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2014	Improving FPGA accelerated tracking with multiple online trained classifiers.	Matthew Jacobsen, Siddarth Sampangi, Yoav Freund, Ryan Kastner
2014	A soft-core processor for finite field arithmetic with a variable word size accelerator.	Aiko Iwasaki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa
2014	Automatic high-level synthesis of multi-threaded hardware accelerators.	Jens Huthmann, Julian Oppermann, Andreas Koch
2014	MAPC: Memory access pattern based controller.	Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrin Cristal, Eduard Ayguad, Mateo Valero
2014	FPGA architecture support for heterogeneous, relocatable partial bitstreams.	Christophe Huriaux, Olivier Sentieys, Russell Tessier
2014	Transparent insertion of latency-oblivious logic onto FPGAs.	Eddie Hung, Tim Todman, Wayne Luk
2014	A scalable, high-performance customized priority queue.	Muhuan Huang, Kevin Lim, Jason Cong
2014	Run-time power gating in hybrid ARM-FPGA devices.	Mohammad Hosseinabady, Jos Luis Nez-Yez
2014	A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms.	Nam Ho, Paul Kaufmann, Marco Platzner
2014	Mixed-architecture process scheduling on tightly coupled reconfigurable computers.	Brandon Kyle Hamilton, Michael Inggs, Hayden Kwok-Hay So
2014	Automated framework for FPGA-based parallel genetic algorithms.	Liucheng Guo, David B. Thomas, Ce Guo, Wayne Luk
2014	THOR - The hardware onion router.	Tim Gneysu, Francesco Regazzoni, Pascal Sasdrich, Marcin Wjcik
2014	Biomedical image processing and reconstruction with dataflow computing on FPGAs.	Frederik Grll, Udo Kebschull
2014	An efficient and flexible host-FPGA PCIe communication library.	Jian Gong, Tao Wang, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu, Jason Cong
2014	Effective FPGA debug for high-level synthesis generated circuits.	Jeffrey B. Goeders, Steven J. E. Wilton
2014	Identifying and placing heterogeneously-sized cluster groupings based on FPGA placement data.	Farnaz Gharibian, Lesley Shannon, Peter Jamieson
2014	Hardware system synthesis from Domain-Specific Languages.	Nithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne
2014	Experimental multi-FPGA GNSS receiver platform.	Fabio Garzia, Alexander Rgamer, Robert Koch, Philipp Neumaier, Ekaterina Serezhkina, Matthias Overbeck, Gnter Rohmer
2014	A highly-efficient and green data flow engine for solving euler atmospheric equations.	Lin Gan, Haohuan Fu, Chao Yang, Wayne Luk, Wei Xue, Oskar Mencer, Xiaomeng Huang, Guangwen Yang
2014	Area implications of memory partitioning for high-level synthesis on FPGAs.	Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides
2014	Caching memcached at reconfigurable network interface.	Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura

926–950 of 3,233← Previous Next →

Comparable venues

Other A*/A conferences filed under the same field of research.