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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2014A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architectures.Christian Fobel, Gary William Grewal, Deborah A. Stacey
2014The LEAP FPGA operating system.Kermin Fleming, Hsin-Jung Yang, Michael Adler, Joel S. Emer
2014Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs.Shane T. Fleming, David B. Thomas
2014Incremental distributed trigger insertion for efficient FPGA debug.Fatemeh Eslami, Steven J. E. Wilton
2014A fast and scalable FPGA damage diagnostic service for R3TOS using BIST cloning technique.Ali Ebrahim, Tughrul Arslan, Xabier Iturbe
2014Evolutionary on-line synthesis of hardware accelerators for software modules in reconfigurable embedded systems.Roland Dobai
2014Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures.Cludio Machado Diniz, Muhammad Shafique, Sergio Bampi, Jrg Henkel
2014Adaptive Dynamic On-chip Memory Management for FPGA-based reconfigurable architectures.Ghada Dessouky, Michael J. Klaiber, Donald G. Bailey, Sven Simon
2014Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration.James J. Davis, Peter Y. K. Cheung
2014A mixed integer linear programming approach for design space exploration in FPGA-based MPSoC.Bouthaina Damak, Rachid Benmansour, Smal Niar, Mouna Baklouti, Mohamed Abid
2014An efficient sparse conjugate gradient solver using a Beneš permutation network.Gary C. T. Chow, Paul Grigoras, Pavel Burovskiy, Wayne Luk
2014Power-efficient re-gridding architecture for accelerating Non-uniform Fast Fourier Transform.Umer I. Cheema, Gregory Nash, Rashid Ansari, Ashfaq A. Khokhar
2014Achieving portability and efficiency over chip heterogeneous multiprocessor systems.Eugene Cartwright, Alborz Sadeghian, Sen Ma, David Andrews
2014Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays.Davor Capalija, Tarek S. Abdelrahman
2014Modulo SDC scheduling with recurrence minimization in high-level synthesis.Andrew Canis, Stephen Dean Brown, Jason Helge Anderson
2014Source-level debugging for FPGA high-level synthesis.Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson
2014Dataflow acceleration of Krylov subspace sparse banded problems.Pavel Burovskiy, Stephen Girdlestone, Craig Davies, Spencer J. Sherwin, Wayne Luk
2014HyPER: A runtime reconfigurable architecture for monte carlo option pricing in the Heston model.Christian Brugger, Christian de Schryver, Norbert Wehn
2014Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing.Oana Boncalo, Alexandru Amaricai, Andrei Hera, Valentin Savin
2014An FPGA hardware acceleration of the indirect calculation of tree lengths method for phylogenetic tree reconstruction.Henry Block, Tsutomu Maruyama
2014Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy.Adrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri
2014Accurate power control and monitoring in ZYNQ boards.Arash Farhadi Beldachi, Jos L. Nez-Yez
2014Portable module relocation and bitstream compression for Xilinx FPGAs.Christian Beckhoff, Dirk Koch, Jim Trresen
2014Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration.Andreas Becher, Florian Bauer, Daniel Ziener, Jrgen Teich
2014A high performance alternating projections image demosaicing hardware.Hasan Azgin, Serkan Yaliman, Ilker Hamzaoglu
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