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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2011Speculative Debug Insertion for FPGAs.Eddie Hung, Steven J. E. Wilton
2011Scalable FRM-SSA SoC Design for the Simulation of Networks with Thousands of Biochemical Reactions in Real Time.Orsalia Georgia Hazapis, Elias S. Manolakos
2011A Radiation Hard Lut Block with Auto-Scrubbing.Kashfia Haque, Paul Beckett
2011A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values.Mark Hamilton, William P. Marnane, Arnaud Tisserand
2011Accelerating Image Analysis for Localization Microscopy with FPGAs.Frederik Grll, Manfred Kirchgessner, Rainer Kaufmann, Michael Hausmann, Udo Kebschull
2011Reducing FPGA Router Run-Time through Algorithm and Architecture.Marcel Gort, Jason Helge Anderson
2011FPGA-Based Acceleration of Block Matching Motion Estimation Techniques.Diego Gonzlez, Guillermo Botella Juan, Soumak Mokheerje, Uwe Meyer-Bse
2011RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC.Diana Ghringer, Stephan Werner, Michael Hbner, Jrgen Becker
2011XDL-Based Module Generators for Rapid FPGA Design Implementation.Subhrashankha Ghosh, Brent E. Nelson
2011Cryptographic Extension for Soft General-Purpose Processors with Secure Key Management.Lubos Gaspar, Viktor Fischer, Lilian Bossuet, Milos Drutarovsk
2011Towards On-the-Fly Incremental Updates for Virtualized Routers on FPGA.Thilan Ganegedara, Hoang Le, Viktor K. Prasanna
2011IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs.Zhe Feng, Naifeng Jing, GengSheng Chen, Yu Hu, Lei He
2011Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs.Brahim Al Farisi, Karel Heyse, Karel Bruneel, Dirk Stroobandt
2011Thwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule Enforcement.Mohammed M. Farag, Lee W. Lerner, Cameron D. Patterson
2011Capacitive Boosting for FPGA Interconnection Networks.Fatemeh Eslami, Mihai Sima
2011Clustered Hierarchical Search Structure for Large-Scale Packet Classification on FPGA.Oguzhan Erdem, Hoang Le, Viktor K. Prasanna
2011Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation.Keisuke Dohi, Yuji Yorita, Yuichiro Shibata, Kiyoshi Oguri
2011Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks.Giorgos Dimitrakopoulos, Christoforos Kachris, Emmanouil Kalligeros
2011Acceleration of Multi-agent Simulation on FPGAs.Lintao Cui, Jing Chen, Yu Hu, Jinjun Xiong, Zhe Feng, Lei He
2011Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms.Jason Cong, Muhuan Huang, Yi Zou
2011A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware.Juan Antonio Clemente, Vincenzo Rana, Donatella Sciuto, Ivan Beretta, David Atienza
2011Novel and Highly Efficient Reconfigurable Implementation of Data Mining Classification Tree.Grigorios Chrysos, Panagiotis Dagritzikos, Ioannis Papaefstathiou, Apostolos Dollas
2011Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA.Yong Cheol Peter Cho, Sungmin Bae, Yongseok Jin, Kevin M. Irick, Vijaykrishnan Narayanan
2011Timing-Driven Routing of High Fanout Nets.Xun Chen, Jianwen Zhu, Minxuan Zhang
2011A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis.Florent Bruguier, Pascal Benoit, Philippe Maurine, Lionel Torres
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