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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2011Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems.Cristiana Bolchini, Antonio Miele, Chiara Sandionigi
2011Performance Failure Prediction Using Built-In Delay Sensors in FPGAs.Vasco Bexiga, Carlos Leong, Jorge Semio, Isabel C. Teixeira, Joo Paulo Teixeira, Mara Dolores Valds, Judit Freijedo, Juan J. Rodrguez-Andina, Fabian Vargas
2011Failure Probability and Fault Observability of SRAM-FPGA Systems.Cinzia Bernardeschi, Luca Cassano, Andrea Domenici
2011Optimizing an Open-Source Processor for FPGAs: A Case Study.Lyonel Barthe, Luis Vitorio Cargnini, Pascal Benoit, Lionel Torres
2011Stress-Aware Module Placement on Reconfigurable Devices.Josef Angermeier, Daniel Ziener, Michael Gla, Jrgen Teich
2011A Low-Cost Sensor for Aging and Late Transitions Detection in Modern FPGAs.Abdulazim Amouri, Mehdi Baradaran Tahoori
2011An Optimized FPGA Implementation of the Modified Space Vector Modulation Algorithm for AC Drives Control.Bogdan Alecsa, Alexandru Onea
2011FPGA Acceleration of the Phylogenetic Parsimony Kernel?Nikolaos Alachiotis, Alexandros Stamatakis
2011A Novel Power Reduction Technique for Block Matching Motion Estimation Hardware.Abdulkadir Akin, Onur Can Ulusel, Tevfik Zafer Ozcan, Gokhan Sayilar, Ilker Hamzaoglu
2011Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic Networks.Rehan Ahmed, Peter Hallschmid
2011Memory Virtualization for Multithreaded Reconfigurable Hardware.Andreas Agne, Marco Platzner, Enno Lbbers
2010High-Performance Integer Factoring with Reconfigurable Devices.Ralf Zimmermann, Tim Gneysu, Christof Paar
2010Self-Test and Adaptation for Random Variations in Reliability.Kenneth M. Zick, John P. Hayes
2010Optimization of Regular Expression Pattern Matching Circuit Using At-Most Two-Hot Encoding on FPGA.SangKyun Yun, KyuHee Lee
2010A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis.Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon
2010Rapid Application Development on Multi-processor Reconfigurable Systems.Linfeng Ye, Jean-Philippe Diguet, Guy Gogniat
2010Dynamically Reconfigurable Vision-Chip Architecture.Maki Yasuda, Minoru Watanabe
2010Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine.Stephen Wray, Wayne Luk, Peter R. Pietzuch
2010Generation of Deterministic MCU/FPGA Hybrid Systems from UML Activities.Ruediger Willenberg, Zamira Daw, Christian Englert, Marcus Vetter
2010An FPGA Based Hybrid Processor Emulation Platform.Qigang Wang, Rolf Kassa, Wenbo Shen, Nelson Ijih, Bhushan Chitlur, Michael Konow, Dong Liu, Arthur Sheiman, Prabhat Gupta
2010Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic.Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2010An FPGA-based Transverse Multibunch Feedback System for Diamond Light Source.Isa Uzun, Mark Heron, Alun Morgan, Guenther Rehm
2010Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options.Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk
2010FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers.David B. Thomas, Wayne Luk
2010Implementing Rainbow Tables in High-End FPGAs for Super-Fast Password Cracking.Kostas Theocharoulis, Ioannis Papaefstathiou, Charalampos Manifavas
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