| 2008 | Reducing interconnection cost in coarse-grained dynamic computing through multistage network. | Ricardo S. Ferreira, Marcone Laure, Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro |
| 2008 | sFPGA - A scalable switch based FPGA architecture and design methodology. | Shakith Fernando, Xiaolei Chen, Yajun Ha |
| 2008 | No-break dynamic defragmentation of reconfigurable devices. | Sndor P. Fekete, Tom Kamphans, Nils Schweer, Christopher Tessars, Jan van der Veen, Josef Angermeier, Dirk Koch, Jrgen Teich |
| 2008 | Customized Reconfigurable Interconnection Networks for multiple application SOCS. | Hongbing Fan, Jason Ernst, Yu-Liang Wu |
| 2008 | Coarse-grained reconfiguration. | Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jrgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jrgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner |
| 2008 | A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. | Andreas Ehliar, Per Karlstrm, Dake Liu |
| 2008 | Loop unrolling and shifting for reconfigurable architectures. | Ozana Silvia Dragomir, Todor P. Stefanov, Koen Bertels |
| 2008 | An symbolic decomposition of functions with multi-valued inputs and outputs for FPGA-based implementation. | Stanislaw Deniziak, Mariusz Wisniewski |
| 2008 | Reconfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systems. | Alexander Danilin, Sergei Sawitzki, Erik Rijshouwer |
| 2008 | Increasing the level of abstraction in FPGA-based designs. | Martin Danek, Jiri Kadlec, Roman Bartosinski, Lukas Kohout |
| 2008 | Fast toggle rate computation for FPGA circuits. | Tomasz S. Czajkowski, Stephen Dean Brown |
| 2008 | An FPGA-based high-speed, low-latency trigger processor for high-energy physics. | Jan de Cuveland, Felix Rettig, Venelin Angelov, Volker Lindenstruth |
| 2008 | Creating unique identifiers on field programmable gate arrays using natural processing variations. | James W. Crouch, Hiren J. Patel, Yong C. Kim, Robert W. Bennington |
| 2008 | Scalable high performance computing on FPGA clusters using message passing. | Eoin Creedon, Michael Manzke |
| 2008 | The hardware application platform of the hartes project. | Immacolata Colacicco, Giacomo Marchiori, Raffaele Tripiccione |
| 2008 | A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. | Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hbner, Jrgen Becker |
| 2008 | A comparison of embedded reconfigurable video-processing architectures. | Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jrgen Teich |
| 2008 | Adaptive precision technique for genetic algorithms. | Gary Chun Tak Chow |
| 2008 | The effect of sparse switch patterns on the area efficiency of multi-bit routing resources in field-programmable gate arrays. | Ping Chen, Andy Ye |
| 2008 | On-the-fly attestation of reconfigurable hardware. | Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa |
| 2008 | Self-recofigurable embedded systems on Spartan-3. | Enrique Cant, Francesc Fons, Mariano Lpez-Garca |
| 2008 | An integrated debugging environment for FPGA computing platforms. | Kevin Camera, Robert W. Brodersen |
| 2008 | Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs. | Betul Buyukkurt, Walid A. Najjar |
| 2008 | Reconfigurable hardware: The holy grail of matching performance with programming productivity. | Claudio Brunelli, Fabio Garzia, Jari Nurmi, Fabio Campi, Damien Picard |
| 2008 | A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck. | Claudio Brunelli, Fabio Garzia, Carmelo Giliberto, Jari Nurmi |