| 2005 | Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis. | Michael Janiaut, Camel Tanougast, Hassan Rabah, Yves Berviller, Christian Mannino, Serge Weber |
| 2005 | A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. | Peter Jamieson, Jonathan Rose |
| 2005 | Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA. | Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri |
| 2005 | Defect Tolerance in Multiple-FPGA Systems. | Zohair Hyder, John Wawrzynek |
| 2005 | PAHLS: Towards Run-Time Synthesis for FPGAs. | Renqiu Huang, Ranga Vemuri |
| 2005 | A Power-Performance Scalable FPGA Using Configurable Voltage Domains and Design Mapping Tool. | Frank Honor |
| 2005 | Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. | Mark Holland, Scott Hauck |
| 2005 | A Flexible Circuit-Switched NOC for FPGA-Based Systems. | Clint Hilton, Brent E. Nelson |
| 2005 | On the Reliability Evaluation of SRAM-Based FPGA Designs. | Olivier Hron, Talal Arnaout, Hans-Joachim Wunderlich |
| 2005 | Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs. | Ronald Hecht, Stephan Kubisch, Andreas Herrholtz, Dirk Timmermann |
| 2005 | MILP-based Placement and Routing for Dataflow Architecture. | Michael B. Healy, Mongkol Ekpanyapong, Sung Kyu Lim |
| 2005 | PGR: A Software Package for Reconfigurable Super-Computing. | Tsuyoshi Hamada, Naohito Nakasato |
| 2005 | Accelerating Molecular Dynamics Simulations With Configurable Circuits. | Yongfeng Gu, Tom Van Court, Martin C. Herbordt |
| 2005 | Real-time Handel-C Based Implementation of DV Decoder. | Marek Gorgon, Slawomir Cichon, Miroslaw Pac |
| 2005 | A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. | Victor Gonalves, Jos T. de Sousa, Fernando M. Gonalves |
| 2005 | A Reconfigurable Instruction Memory Hierarchy for Embedded Systems. | Zhiguo Ge, Hock-Beng Lim, Weng-Fai Wong |
| 2005 | Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks. | Antonio Garca, Javier Ramrez, Uwe Meyer-Bse, Encarnacin Castillo, Antonio Lloris-Ruz |
| 2005 | A Programmable Logic Architecture for Prototyping Clockless Circuits. | Laurent Fesquet, Marc Renaudin |
| 2005 | Snow 2.0 IP Core for Trusted Hardware. | Wenhai Fang, Thomas Johansson, Lambert Spaanenburg |
| 2005 | Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. | Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk |
| 2005 | FPGA-Aware Garbage Collection in Java. | Philippe Faes, Mark Christiaens, Dries Buytaert, Dirk Stroobandt |
| 2005 | Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. | Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides |
| 2005 | Dual FiXed-point : An Efficient Alternative to Floating-point Computation for DSP applications. | Chun Te Ewe |
| 2005 | A Dynamically Reconfigurable Bluetooth Base Band Unit. | John Esquiagola, Guilherme Ozari, Marcio Yukio Teruya, Marius Strum, Jiang Chau Wang |
| 2005 | An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning. | Pedro M. Domingos, Fernando M. Silva, Horcio C. Neto |