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Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2005Efficient Execution on Reconfigurable Devices Using Concepts of Pipelining.Florian Dittmann
2005CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools.Robert G. Dimond, Oskar Mencer, Wayne Luk
2005Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs.Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis
2005High Performance Stereo Computation Architecture.Javier Daz, Eduardo Ros, Sonia Mota, Eva M. Ortigosa, Begoa del Pino
2005Finite Field Division Implementation.Jean-Pierre Deschamps, Gustavo Sutter
2005Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs.Kristof Denolf, Adrian Chirila-Rus, Robert D. Turney, Paul R. Schumacher, Kees A. Vissers
2005A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware.Klaus Danne, Marco Platzner
2005A Novel Toolset for the Development of FPGA-like Reconfigurable Logic.Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki
2005LAMP: A Tool Suite for Families of FPGA-Based Application Accelerators.Tom Van Court, Martin C. Herbordt
2005An Approach to Scalable Molecular Dynamics Simulation Using Supercomputing Adaptive Processing Elements.Luis E. Cordova, Duncan A. Buell
2005Parameterized Logic Power Consumption Models for FPGA based Systems.Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides
2005High Speed / Low Power Architectures for the Finite Radon Transform.Shrutisagar Chandrasekaran, Abbes Amira
2005Generalizing Square Attack using Side-Channels of an AES Implementation on an FPGA.Vincent Carlier, Herv Chabanne, Emmanuelle Dottax, Herv Pelletier
2005Area-Efficient 2-D Shift-Variant Convolvers for FPGA-based Digital Image Processing.Francisco Cardells-Tormo, Pep-Lluis Molinet, Jordi Sempere-Agull, Luis Baldez, Marc Bautista-Palacios
2005Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes.Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
2005FPGA Interconnect Fault tolerance.Nicola Campregher
2005Magnetic remanent memory structures for dynamically reconfigurable fine grain FPGA.Nicolas Bruchon, Gaston Cambon, Lionel Torres, Gilles Sassatelli
2005Heterogeneity Exploration for Multiple 2D Filter Designs.Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides
2005DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices.Christophe Bobda, Ali Ahmadinia, Mateusz Majer, Jrgen Teich, Sndor P. Fekete, Jan van der Veen
2005Next Generation Architectures and CAD for Power Aware Programmable Fabrics.Rajarshee P. Bharadwaj
2005Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors.Pascal Benoit, Jrgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon
2005Configurable Hardware/Software Architecture for Data Acquisition: Implementation on FPGA.Marc Bautista-Palacios, Luis Baldez, Jordi Sempere-Agull, Atil Herms-Berenguer, Francisco Cardells-Tormo, Pep-Lluis Molinet
2005Hierarchical Placement for Large-scale FPAA.I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, David V. Anderson
2005Fast FPGA Placement using Space-filling Curve.Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy
2005Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications.Sajid Baloch, Imran Ahmed, Tughrul Arslan, Adrian Stoica
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