| 2011 | Investigation of multi cell upset in sequential logic and validity of redundancy technique. | Taiki Uemura, Takashi Kato, Hideya Matsuyama, Keiji Takahisa, Mitsuhiro Fukuda, Kichiji Hatanaka |
| 2011 | A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. | Taiga Takata, Yusuke Matsunaga |
| 2011 | Rise of the hardware Trojans. | Berk Sunar |
| 2011 | An intellectual property core to detect task schedulling-related faults in RTOS-based embedded systems. | Dhiego Silva, Letcia Maria Veiras Bolzani, Fabian Vargas |
| 2011 | A novel radiation tolerant SRAM design based on synergetic functional component separation for nanoscale CMOS. | Yuriy Shiyanovskii, Aravind Rajendran, Christos A. Papachristou |
| 2011 | An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. | Matthias Sauer, Victor Tomashevich, Jrg Mller, Matthew Lewis, Andreas Spilla, Ilia Polian, Bernd Becker, Wolfram Burgard |
| 2011 | Estimation of component criticality in early design steps. | Matthias Sauer, Alejandro Czutro, Ilia Polian, Bernd Becker |
| 2011 | An analytical model for the calculation of the Expected Miss Ratio in faulty caches. | Daniel Snchez, Yiannakis Sazeides, Juan L. Aragn, Jos M. Garca |
| 2011 | Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wire. | Ronak Salamat, Hamid R. Zarandi |
| 2011 | On graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution units. | Rance Rodrigues, Sandip Kundu |
| 2011 | On graceful degradation of microprocessors in presence of faults via resource banking. | Rance Rodrigues, Sandip Kundu |
| 2011 | Self-checking test circuits for latches and flip-flops. | Renato P. Ribas, Yuyang Sun, Andr Incio Reis, Andr Ivanov |
| 2011 | Noise margin, critical charge and power-delay tradeoffs for SRAM design. | Aravind Rajendran, Yuriy Shiyanovskii, Frank Wolff, Christos A. Papachristou |
| 2011 | Reduced overhead soft error mitigation using error control coding techniques. | V. Prasanth, Virendra Singh, Rubin A. Parekhji |
| 2011 | Multi-level secure JTAG architecture. | Luke Pierce, Spyros Tragoudas |
| 2011 | Towards functional-safe timing-dependable real-time architectures. | Marco Paolieri, Riccardo Mariani |
| 2011 | Real time cross-layer adaptation for minimum energy wireless image transport using bit error rate control. | Jayaram Natarajan, Shreyas Sen, Abhijit Chatterjee |
| 2011 | AKARI-X: A pseudorandom number generator for secure lightweight systems. | Honorio Martn, Enrique San Milln, Luis Entrena, Julio Csar Hernndez Castro, Pedro Peris-Lopez |
| 2011 | Countermeasures against fault attacks: The good, the bad, and the ugly. | Paolo Maistri |
| 2011 | Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies. | Madalin Neagu, Liviu Miclea, Joan Figueras |
| 2011 | Variations of fault manifestation during Burn-In - A case study on industrial SRAM test results. | Michael Linder, Alfred Eder, Klaus Oberlnder, Martin Huch |
| 2011 | A side channel attack countermeasure using system-on-chip power profile scrambling. | Armin Krieg, Johannes Grinschgl, Christian Steger, Reinhold Weiss, Josef Haid |
| 2011 | Loopback output router for reliable Network on Chip. | Cdric Killian, Camel Tanougast, Fabrice Monteiro, Abbas Dandache |
| 2011 | Control-flow error recovery using commodity multi-core architecture features. | Navid Khoshavi, Hamid R. Zarandi, Mohammad Maghsoudloo |
| 2011 | Modeling and mitigating NBTI in nanoscale circuits. | Seyab Khan, Said Hamdioui |