| 2011 | Detection of Trojan HW by using hidden information on the system. | Osnat Keren, Ilya Levin, Vladimir Sinelnikov |
| 2011 | Error correction encoding for multi-threshold capture mechanism. | Kedar Karmarkar, Spyros Tragoudas |
| 2011 | High-level synthesis for multi-cycle transient fault tolerant datapaths. | Tomoo Inoue, Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara |
| 2011 | Soft error correction in embedded storage elements. | Michael E. Imhof, Hans-Joachim Wunderlich |
| 2011 | Generic BIST architecture for testing of content addressable memories. | Hayk T. Grigoryan, Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian |
| 2011 | Generalized parity-check matrices for SEC-DED codes with fixed parity. | Valentin Gherman, Samuel Evain, Nathaniel Seymour, Yannick Bonhomme |
| 2011 | Software-based control flow error detection and correction using branch triplication. | Nahid Farhady Ghalaty, Mahdi Fazeli, Hossein Izadi Rad, Seyed Ghassem Miremadi |
| 2011 | Memory BIST with address programmability. | Aymen Fradi, Michael Nicolaidis, Lorena Anghel |
| 2011 | An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities. | Josep Torras Flaquer, Jean-Marc Daveau, Lirida A. B. Naviner, Philippe Roche |
| 2011 | Matrix control-flow algorithm-based fault tolerance. | Ronaldo Rodrigues Ferreira, lvaro Freitas Moreira, Luigi Carro |
| 2011 | ICT: Interface software for the characterization and test of mixed-signal power cores. | Jorge O. M. Esteves, Tiago H. Moita, Carlos B. Almeida, Marcelino B. Santos |
| 2011 | A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories. | Enrico Costenaro, Massimo Violante, Dan Alexandrescu |
| 2011 | Variability-aware task mapping strategies for many-cores processor chips. | Fabien Chaix, Gilles Bizot, Michael Nicolaidis, Nacer-Eddine Zergainoh |
| 2011 | A verification strategy for fault-detection and fault-tolerance circuits. | Gabriele Boschi, Riccardo Mariani, Stefano Lorenzini |
| 2011 | A reliable fault classifier for dependable systems on SRAM-based FPGAs. | Cristiana Bolchini, Chiara Sandionigi, Luca Fossati, David Merodio Codinachs |
| 2011 | Fault attack resistant deterministic random bit generator usable for key randomization. | Eberhard Bhl, Paul Duplys |
| 2011 | An effective methodology for on-line testing of embedded microprocessors. | Paolo Bernardi, Lyl M. Ciganda, Ernesto Snchez, Matteo Sonza Reorda |
| 2011 | Fail-safety in core-based system design. | Rafal Baranowski, Hans-Joachim Wunderlich |
| 2011 | An on-line memory state validation using shadow memory cloning. | Mikhail Baklashov |
| 2011 | New reliability mechanisms in memory design for sub-22nm technologies. | Nivard Aymerich, A. Asenov, Andrew R. Brown, Ramon Canal, Binjie Cheng, Joan Figueras, Antonio Gonzlez, Enric Herrero, S. Markov, Miguel Miranda, Peyman Pouyan, Tanaus Ramrez, Antonio Rubio, Elena I. Vatajelu, Xavier Vera, Xingsheng Wang, Paul Zuber |
| 2011 | Selective fault tolerance for finite state machines. | Michael Augustin, Michael Gssel, Rolf Kraemer |
| 2011 | Internal model control for a self-tuning Delay-Locked Loop in UWB communication systems. | Rshdee Alhakim, Emmanuel Simeu, Kosai Raoof |
| 2011 | A comprehensive soft error analysis methodology for SoCs/ASICs memory instances. | Dan Alexandrescu |
| 2011 | RVC-based time-predictable faulty caches for safety-critical systems. | Jaume Abella, Eduardo Quiones, Francisco J. Cazorla, Mateo Valero, Yanos Sazeides |
| 2011 | Towards improved survivability in safety-critical systems. | Jaume Abella, Francisco J. Cazorla, Eduardo Quiones, Arnaud Grasset, Sami Yehia, Philippe Bonnot, Dimitris Gizopoulos, Riccardo Mariani, Guillem Bernat |