| 2005 | Strategic Use of SEE Mitigation Techniques for the Development of the ESA Microprocessors: Past, Present and Future. | Andre L. R. Pouponnot |
| 2005 | On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. | Michele Portolan, Rgis Leveugle |
| 2005 | How to Cope with SEU/SET at System Level?. | Michel Pignol |
| 2005 | Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems. | Ishwar Parulkar, Robert Cypher |
| 2005 | On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization. | Martin Omaa, O. Losco, Cecilia Metra, Andrea Pagni |
| 2005 | On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations. | Vitalij Ocheretnij, G. Kouznetsov, Ramesh Karri, Michael Gssel |
| 2005 | Coding Techniques for Low Switching Noise in Fault Tolerant Busses. | Andr K. Nieuwland, Atul Katoch, Daniele Rossi, Cecilia Metra |
| 2005 | Design for Mitigation of Single Event Effects. | Michael Nicolaidis |
| 2005 | Power-Balanced Self Checking Circuits for Cryptographic Chips. | Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev |
| 2005 | Hardening Techniques against Transient Faults for Asynchronous Circuits. | Yannick Monnet, Marc Renaudin, Rgis Leveugle |
| 2005 | Security Testing for Hardware Products: The Security Evaluations Practice. | Alain Merle, Jessy Cldire |
| 2005 | Fast, Parallel Two-Rail Code Checker with Enhanced Testability. | Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou |
| 2005 | Scrubbing and Partitioning for Protection of Memory Systems. | Riccardo Mariani, Gabriele Boschi |
| 2005 | Integrating BIST Techniques for On-Line SoC Testing. | Alberto Manzone, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Ernesto Snchez, Matteo Sonza Reorda |
| 2005 | DFT Assisted Built-In Soft Error Resilience. | T. M. Mak, Subhasish Mitra, Ming Zhang |
| 2005 | Does It Mean Less Testing for Self Calibrating Design?. | T. M. Mak |
| 2005 | Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. | Celia Lpez-Ongil, Mario Garca-Valderas, Marta Portela-Garca, Luis Entrena-Arrontes |
| 2005 | On-Line Testing for Secure Implementations: Design and Validation. | Rgis Leveugle, Yervant Zorian, Luca Breveglieri, Andr K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert |
| 2005 | A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations. | Rgis Leveugle |
| 2005 | Introduction to the Special Session on Secure Implementations. | Rgis Leveugle |
| 2005 | Modeling of Transients Caused by a Laser Attack on Smart Cards. | Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache |
| 2005 | Introduction to Fault Attacks on Smartcard. | Antoine Lemarechal |
| 2005 | On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study. | Cristiano Lazzari, Lorena Anghel, Ricardo A. L. Reis |
| 2005 | A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory. | Andrzej Krasniewski |
| 2005 | A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features. | Ren Kothe, Christian Galke, Heinrich Theodor Vierhaus |