| 2005 | Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. | Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy |
| 2005 | Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. | Kentaroh Katoh, Abderrahim Doumar, Hideo Ito |
| 2005 | A Review of DASIE Code Family: Contribution to SEU/MBU Understanding. | Guillaume Hubert, Nadine Buard, Ccile Weulersse, Thierry Carrire, Marie-Catherine Palau, Jean-Marie Palau, Damien Lambert, Jacques Baggio, Frederic Wrobel, Frdric Saign, Rmi Gaillard |
| 2005 | Analytical Semi-Empirical Model for SER Sensitivity Estimation of Deep-Submicron CMOS Circuits. | Tino Heijmen |
| 2005 | On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST). | Donghoon Han, Selim Sermet Akbay, Soumendu Bhattacharya, Abhijit Chatterjee, William R. Eisenstadt |
| 2005 | Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM. | Balkaran S. Gill, Michael Nicolaidis, Christos A. Papachristou |
| 2005 | Analyzing the Effectiveness of Fault Hardening Procedures. | Piotr Gawkowski, Janusz Sosnowski, B. Radko |
| 2005 | Electrical Modeling for Laser Testing with Different Pulse Durations. | Alexandre Douin, Vincent Pouget, Dean Lewis, Pascal Fouillat, Philippe Perdu |
| 2005 | Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits. | Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra |
| 2005 | Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. | Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy |
| 2005 | Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing. | Yves Crouzet, Jacques Henri Collet, Jean Arlat |
| 2005 | Process Variation Tolerant Online Current Monitor for Robust Systems. | Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy |
| 2005 | On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. | Jos Manuel Cazeaux, Daniele Rossi, Martin Omaa, Cecilia Metra, Abhijit Chatterjee |
| 2005 | Design of a Self Checking Reed Solomon Encoder. | Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano |
| 2005 | Overview of Soft Errors Issues in Aerospace Systems. | Christian Bolat, Gerard Colas |
| 2005 | Side-Channel Issues for Designing Secure Hardware Implementations. | Lejla Batina, Nele Mentens, Ingrid Verbauwhede |
| 2005 | Simulation and Mitigation of Single Event Effects. | Lorena Anghel, Michael Nicolaidis |
| 2005 | Evaluation of SET and SEU Effects at Multiple Abstraction Levels. | Lorena Anghel, Rgis Leveugle, Pierre Vanhauwaert |
| 2005 | A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. | Bartomeu Alorda, Sebasti A. Bota, Jaume Segura |
| 2005 | Heavy Ion Effects on Configuration Logic of Virtex FPGAs. | Monica Alderighi, A. Candelori, Fabio Casini, Sergio D'Angelo, Marcello Mancini, Alessandro Paccagnella, Sandro Pastore, Giacomo R. Sechi |
| 2005 | Modeling Soft-Error Susceptibility for IP Blocks. | Robert C. Aitken, Betina Hold |
| 2004 | Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm. | Hamid R. Zarandi, Seyed Ghassem Miremadi, Hamid Sarbazi-Azad |
| 2004 | Testing of Hard Faults in Simultaneous Multithreaded Processors. | Eric F. Weglarz, Kewal K. Saluja, T. M. Mak |
| 2004 | Single-Output Embedded Checkers for Systematic Unordered Codes. | Steffen Tarnick |
| 2004 | Necessary and Sufficient Conditions for the Existence of Totally Self-Checking Circuits. | Valerij V. Saposhnikov, Vladimir V. Saposhnikov, Andrej A. Morosov, Michael Gssel |