| 2012 | Low power programmable PRPG with enhanced fault coverage gradient. | Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski |
| 2012 | Impact of Radial defect clustering on 3D stacked IC yield from wafer to wafer stacking. | Eshan Singh |
| 2012 | Systematic defect screening in controlled experiments using volume diagnosis. | B. Seshadri, P. Gupta, Y. T. Lin, Bruce Cory |
| 2012 | Functional test of small-delay faults using SAT and Craig interpolation. | Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker |
| 2012 | DART: Dependable VLSI test architecture and its implementation. | Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura |
| 2012 | Packet-based JTAG for remote testing. | Michele Portolan |
| 2012 | Capacitive sensing testability in complex memory devices. | Kenneth P. Parker |
| 2012 | Scan test of die logic in 3D ICs using TSV probing. | Brandon Noia, Shreepad Panth, Krishnendu Chakrabarty, Sung Kyu Lim |
| 2012 | How are failure modes, defect types and test methods changing for 32nm/28nm technologies and beyond? | Phil Nigh |
| 2012 | An ATE architecture for implementing very high efficiency concurrent testing. | Takahiro Nakajima, Takeshi Yaguchi, Hajime Sugimura |
| 2012 | Improving test compression by retaining non-pivot free variables in sequential linear decompressors. | Sreenivaas S. Muthyala, Nur A. Touba |
| 2012 | Driver sharing challenges for DDR4 high-volume testing with ATE. | Jose Moreira, Marc Moessinger, Koji Sasaki, Takayuki Nakamura |
| 2012 | Low cost high-speed test data acquisition: Accurate period estimation driven signal reconstruction using incoherent subsampling. | Thomas Moon, Hyun Woo Choi, Abhijit Chatterjee |
| 2012 | A design flow to maximize yield/area of physical devices via redundancy. | Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta |
| 2012 | FALCON: Rapid statistical fault coverage estimation for complex designs. | Shahrzad Mirkhani, Jacob A. Abraham, Toai Vo, Hong Shin Jun, Bill Eklow |
| 2012 | The DFT challenges and solutions for the ARM Cortex™-A15 Microprocessor. | Teresa L. McLaurin, Frank Frederick, Rich Slobodnik |
| 2012 | Vulnerability-based Interleaving for Multi-Bit Upset (MBU) protection in modern microprocessors. | Michail Maniatakos, Maria K. Michael, Yiorgos Makris |
| 2012 | On modeling faults in FinFET logic circuits. | Yuxi Liu, Qiang Xu |
| 2012 | On efficient silicon debug with flexible trace interconnection fabric. | Xiao Liu, Qiang Xu |
| 2012 | A unified method for parametric fault characterization of post-bond TSVs. | Yu-Hsiang Lin, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng, Stephen K. Sunter |
| 2012 | Design validation of RTL circuits using evolutionary swarm intelligence. | Min Li, Kelson Gent, Michael S. Hsiao |
| 2012 | Event-driven framework for configurable runtime system observability for SOC designs. | Jong Chul Lee, Faycel Kouteib, Roman Lysecky |
| 2012 | Test/ATE vision 2020 - Entrepreneurship in test CEO panel. | Ken Lanier |
| 2012 | Integrated optimization of semiconductor manufacturing: A machine learning approach. | Nathan Kupp, Yiorgos Makris |
| 2012 | Spatial estimation of wafer measurement parameters using Gaussian process models. | Nathan Kupp, Ke Huang, John M. Carulli Jr., Yiorgos Makris |