Skip to content

IEEE International Test Conference

ITC

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

4,920

1981–2025

Papers per year

1981207 peak2025

ITC papers

4,920 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2003H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing.David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Kim, Anil Sabbavarapu, Talal Jaber, Pete Johnson, Dale March, Greg Parrish
2003Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis.Kaijie Wu, Ramesh Karri
2003Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal.Qingwei Wu, Michael S. Hsiao
2003Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie.Derek Wright, Manoj Sachdev
2003X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture.Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin
2003Designed -in-diagnostics: A new optical method.Keneth R. Wilsher
2003Adapting JTAG for AC Interconnect Testing.Lee Whetsel
2003ATE-Customer Perspectives & Requirements Panel.Donald L. Wheater
2003Multi-GB/s IC Test Challenges and Solutions.Burnell G. West
2003Simultaneous Bidirectional Test Data Flow for a Low-cost Wafer Test Strategy.Burnell G. West
2003PXI: A Solution For Board Functional Test?Jim Webster
2003Mitigating the Effects of The DUT Interface board and Test System Parasitics in Gigabit-Plus Measurements.Thomas P. Warwick
2003An Efficient and Effective Methodology on the Multiple Fault Diagnosis.Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski
2003Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects.Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
2003Fault Pattern Oriented Defect Diagnosis for Memories.Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang
2003A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs.Seongmoon Wang, Srimat T. Chakradhar
2003Future Challenges for MEMS Failure Analysis.Jeremy A. Walraven
2003Tools and Techniques for Failure Analysis and Qualification of MEMS.Jeremy A. Walraven
2003Failure Mechanisms in MEMS.Jeremy A. Walraven
2003Introduction to Applications and Industries for Microelectromechanical Systems (MEMS).Jeremy A. Walraven
2003The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data.Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson, Peter Harrod
2003An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips.Tom Waayers
2003ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume.Harald P. E. Vranken, Friedrich Hapke, Soenke Rogge, Domenico Chindamo, Erik H. Volkerink
2003Production Deployment of a Fast Transient Testing Methodology for Analog Circuits : Case Study and Results.Ramakrishna Voorakaranam, Randy Newby, Sasikumar Cherubal, Bob Cometta, Thomas Kuehl, David M. Majernik, Abhijit Chatterjee
2003Progressive Bridge Identification.Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton
1,9511,975 of 4,920← PreviousNext →

Comparable venues

Other A*/A conferences filed under the same field of research.