| 2002 | Testing the Tester: Specification and Validation Approaches. | John C. Johnson |
| 2002 | An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes. | Zhigang Jiang, Sandeep K. Gupta |
| 2002 | Integration of SRAM Redundancy into Production Test. | Jayasanker Jayabalan, Juraj Povazanec |
| 2002 | Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique. | Vishal Jain, John A. Waicukauski |
| 2002 | An Open Architecture for Semiconductor Test: Enablers and Challenges. | Mark Jagiela |
| 2002 | Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. | Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty |
| 2002 | Optimal BIST Using an Embedded Microprocessor. | Sungbae Hwang, Jacob A. Abraham |
| 2002 | Compensation of Transmission Line Loss for Gbit/s Test on ATEs. | Wolfram Humann |
| 2002 | Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. | Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan |
| 2002 | An Effective Diagnosis Method to Support Yield Improvement. | Camelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg |
| 2002 | Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines. | Dale E. Hoffman |
| 2002 | Test Coverage: What Does It Mean When a Board Test Passes?. | Kathy Hird, Kenneth P. Parker, Bill Follis |
| 2002 | DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs. | Osamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Akihito Tohata, Nobuaki Otsuka |
| 2002 | GHz Testing and Its Fuzzy Targets. | Chuck Hawkins, Jaume Segura |
| 2002 | Application of High-Quality Built-In Test to Industrial Designs. | Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo |
| 2002 | Test and Evaluation of Multiple Embedded Mixed-Signal Test Cores. | Mohamed M. Hafed, Gordon W. Roberts |
| 2002 | Re-Using DFT Logic for Functional and Silicon Debugging Test. | Xinli Gu, Weili Wang, Kevin Li, Heon C. Kim, Sung Soo Chung |
| 2002 | Integrating DFT in the Physical Synthesis Flow. | Los Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur |
| 2002 | Testing Finite State Machines Based on a Structural Coverage Metric . | Sezer Gren, F. Joel Ferguson |
| 2002 | Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. | Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici |
| 2002 | Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. | Sandeep Kumar Goel, Bart Vermeulen |
| 2002 | Effective and Efficient Test Architecture Design for SOCs. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2002 | Is Scan (Alone) Sufficient to Test Today?s Microprocessors? Not Quite, but We Can?t Get the Job Done Without It. | Grady Giles |
| 2002 | Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume. | M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor |
| 2002 | Realistic Spring Probe Testing Methods and Results. | David Gessel, Alexander H. Slcoum, Alexander D. Sprunt, Scott Ziegenhagen |