| 2002 | Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines. | Bill Bottoms |
| 2002 | Power Driven Chaining of Flip-Flops in Scan Architectures. | Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch |
| 2002 | Fault Tuples in Diagnosis of Deep-Submicron Circuits. | Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels |
| 2002 | Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits. | Jayanta Bhadra, Narayanan Krishnamurthy |
| 2002 | An Efficient Linear Time Algorithm for Scan Chain Optimization and Repartitioning. | David Berthelot, Samit Chaudhuri, Hamid Savoj |
| 2002 | Improved IDDQ Testing with Empirical Linear Prediction. | David I. Bergman, Hans Engler |
| 2002 | Static Analysis of SEU Effects on Software Applications. | Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto |
| 2002 | Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor . | Dawit Belete, Ashutosh Razdan, William Schwarz, Rajesh Raina, Christopher Hawkins, Jeff Morehead |
| 2002 | Automatic Scan Insertion and Test Generation for Asynchronous Circuits. | Frank te Beest, Ad M. G. Peeters, Marc Verra, Kees van Berkel, Hans G. Kerkhoff |
| 2002 | Pseudo Random Patterns Using Markov Sources for Scan BIST. | Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz |
| 2002 | Selective Optimization of Test for Embedded Flash Memory. | Roger Barth |
| 2002 | Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model. | Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh |
| 2002 | Efficient Design of System Test: A Layered Architecture. | Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei |
| 2002 | Facilitating Rapid First Silicon Debug. | Hari Balachandran, Kenneth M. Butler, Neil Simpson |
| 2002 | Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. | Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina |
| 2002 | Across the Great Divide: Examination of Simulation Data with Actual Silicon Waveforms Improves Device Characterization and Production Test Development. | Tom Austin, Charisma Canlas, Brady Morgan, Jorge L. Rodriguez |
| 2002 | WCDMA Testing with a Baseband/IF Range AWG. | Koji Asami, Yasuo Furukawa, Michael Purtell, Motoo Ueda, Karl Watanabe, Toshifumi Watanabe |
| 2002 | Mixed-Signal BIST: Fact or Fiction. | Karim Arabi |
| 2002 | The Yield of Test Outsourcing. | Davide Appello |
| 2002 | Is It Rocket Science? | Anthony P. Ambler |
| 2002 | Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs. | Bartomeu Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura |
| 2002 | Verifying Properties Using Sequential ATPG. | Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab |
| 2001 | : Identifying redundant gate replacements in verification by error modeling. | Zeljko Zilic, Katarzyna Radecka |
| 2001 | A validation fault model for timing-induced functional errors. | Qiushuang Zhang, Ian G. Harris |
| 2001 | On-line testing and recovery in TMR systems for real-time applications. | Shu-Yi Yu, Edward J. McCluskey |