| 2001 | Split timing mode (STM)-answer to dual frequency domain testing. | A. T. Sivaram |
| 2001 | Detecting delay faults using power supply transient signal analysis. | Abhishek Singh, Chintan Patel, Shirong Liao, James F. Plusquellic, Anne E. Gattiker |
| 2001 | Space and time compaction schemes for embedded cores. | Ozgur Sinanoglu, Alex Orailoglu |
| 2001 | At-speed logic BIST using a frozen clock testing strategy. | Jongshin Shin, Xiaoming Yu, Elizabeth M. Rudnick, Miron Abramovici |
| 2001 | An approach to consistent jitter modeling for various jitter aspects and measurement methods. | Masashi Shimanouchi |
| 2001 | Testing of critical paths for delay faults. | Manish Sharma, Janak H. Patel |
| 2001 | Memory built-in self-repair using redundant words. | Volker Schber, Steffen Paul, Olivier Picot |
| 2001 | An analysis of power reduction techniques in scan testing. | Jayashree Saxena, Kenneth M. Butler, Lee Whetsel |
| 2001 | An evaluation of defect-oriented test: WELL-controlled low voltage test. | Yasuo Sato, Masaki Kohno, Toshio Ikeda, Iwao Yamazaki, Masato Hamamoto |
| 2001 | Improved wafer-level spatial analysis for I_DDQ limit setting. | Sagar S. Sabade, D. M. H. Walker |
| 2001 | Boolean and current detection of MOS transistor with gate oxide short. | Michel Renovell, Jean Marc Gallire, Florence Azas, Serge Bernard, Yves Bertrand |
| 2001 | IS-FPGA : a new symmetric FPGA architecture with implicit scan. | Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 2001 | Too much delay fault coverage is a bad thing. | Jeff Rearick |
| 2001 | Fast test generation for circuits with RTL and gate-level views. | Srivaths Ravi, Niraj K. Jha |
| 2001 | On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. | Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | A method to enhance the fault coverage obtained by output response comparison of identical circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | Bitline contacts in high density SRAMs: design for testability and stressability. | Harold Pilo, R. Dean Adams, Robert E. Busch, Eric A. Nelson, Geoerge E. Rudgers |
| 2001 | Practical application of energy consumption ratio test. | Eric Peterson, Wanli Jiang |
| 2001 | Power supply transient signal integration circuit. | Chintan Patel, Fidel Muradali, James F. Plusquellic |
| 2001 | Exact path delay grading with fundamental BDD operations. | Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas |
| 2001 | Pin electronics IC for high speed differential devices. | Atsushi Oshima, John Poniatowski, Toshihiro Nomura |
| 2001 | Testability implications in low-cost integrated radio transceivers: a Bluetooth case study. | Christian Olgaard, Sule Ozev, Alex Orailoglu |
| 2001 | Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation. | Nicola Nicolici, Bashir M. Al-Hashimi |
| 2001 | Test and repair of large embedded DRAMs. 2. | Eric A. Nelson, Jeffrey H. Dreibelbis, Roderick McConnell |
| 2001 | Cost evaluation of coverage directed test generation for the IBM mainframe. | Gilly Nativ, Steven Mittermaier, Shmuel Ur, Avi Ziv |