| 1997 | Impact of Partial Reset on Fault Independent Testing and BIST. | Huy Nguyen, Abhijit Chatterjee, Rabindra K. Roy |
| 1997 | Optimal Clock Period for Synthesized Data Paths. | A. R. Naseer, M. Balakrishnan, Anshul Kumar |
| 1997 | A New Methodology for the Design of Asynchronous Digital Circuits. | K. Nanda, S. K. Desai, S. K. Roy |
| 1997 | Media Processors. | Sunil Nanda |
| 1997 | A Visual Approach for Asynchronous Circuit Synthesis. | Radhakrishna Nagalla, Graham R. Hellestrand |
| 1997 | Some Recent Advances in Software and Hardware Logic Simulation. | Rajeev Murgai, Masahiro Fujita |
| 1997 | A 2.5 V 10 bit SAR ADC. | Subhashish Mukherjee, C. Srinivasan, Vivek Pawar, Sumeet Mathur, Kiran Godbole, Eric Soenen |
| 1997 | On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. | Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri |
| 1997 | Asynchronous Implementation of Synchronous Esterel Specifications. | Raj S. Mitra, Bishnupriya Bhattacharya, Luciano Lavagno |
| 1997 | T6: C++/java(Tm)/unix. | P. Meyer |
| 1997 | Input Pattern Classification for Detection of Stuck-ON and Bridging Faults Using I | Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana |
| 1997 | Formal Techniques for Hardware Allocation. | Jos M. Mendas, Romn Hermida, Milagros Fernndez |
| 1997 | T3: Physical Design. | Dinesh P. Mehta, Naveed A. Sherwani, A. Bariya |
| 1997 | A Simulation Methodology for Software Energy Evaluation. | Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin |
| 1997 | Synthesis for Testability by Two-Clock Control. | Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth |
| 1997 | Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1997 | Interconnection Delay and Clock Cycle Selection in High Level Synthesis. | Hortensia Mecha, Milagros Fernndez |
| 1997 | Parallel VLSI-Routing Models for Polymorphic Processors Array. | Pinaki Mazumdar |
| 1997 | A Self-Biased High Performance Folded Cascode CMOS Op-Amp. | Pradip Mandal, V. Visvanathan |
| 1997 | Design Space Exploration for Data Path Synthesis. | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose |
| 1997 | FPGA Implementation of Median Filter. | R. Maheshwari, S. S. S. P. Rao, E. G. Poonach |
| 1997 | Shift Switching with Domino Logic: Asynchronous VLSI Comparator Schemes. | Ron Lin |
| 1997 | Channel and Switchbox Routing with Minimized Crosstalk - A Parallel Genetic Algorithm Approach. | Jens Lienig |
| 1997 | Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. | Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee |
| 1997 | Allocation of FIFO Structures in RTL Data Paths. | Heman Khanna, M. Balakrishnan |