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International Conference on VLSI Design

VLSID

National

CORE rank

CORE rank (raw)

National: India

Fields of research

Distributed Computing and Systems Software

Papers indexed

3,530

1992–2026

Papers per year

1992175 peak2026

VLSID papers

3,530 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2008On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set.Hafizur Rahaman, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya
2008Fast Congestion Aware Routing for Pin Assignment.Shashank Prasad
2008On the Use of Hash Tables for Efficient Analog Circuit Synthesis.Almitra Pradhan, Ranga Vemuri
2008A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions.Nagaraju Pothineni, Anshul Kumar, Kolin Paul
2008Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors.Nagaraju Pothineni, Anshul Kumar, Kolin Paul
2008On Common-Mode Skewed-Load and Broadside Tests.Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu
2008Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity.Irith Pomeranz, Sudhakar M. Reddy
2008Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths.Irith Pomeranz, Sudhakar M. Reddy
2008Oversampling Analog-to-Digital Converter Design.Shanthi Pavan, Nagendra Krishnapura
2008Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt
2008Adaptive Signal Scaling Driven Critical Path Modulation for Low Power Baseband OFDM Processors.Muhammad Mudassar Nisar, Rajarajan Senguttuvan, Abhijit Chatterjee
2008Throughput Efficient Parallel Implementation of SPIHT Algorithm.Anilkumar V. Nandi, R. M. Banakar
2008Standards in EDA: An Introduction.Nagi Naganathan
2008Exploring the Processor and ISA Design for Wireless Sensor Network Applications.Shashidhar Mysore, Banit Agrawal, Frederic T. Chong, Timothy Sherwood
2008Variability-Tolerant Register-Transfer Level Synthesis.Anish Muttreja, Srivaths Ravi, Niraj K. Jha
2008Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects.Anish Muttreja, Prateek Mishra, Niraj K. Jha
2008Chaos-Modulated Ramp IC for EMI Reduction in PWM Buck Converters- Design and Analysis of Critical Issues.Rupam Mukherjee, Amit Patra, Soumitro Banerjee
2008Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance.Jeff Mueller, Resve A. Saleh
2008Testing Flash Memories for Tunnel Oxide Defects.Mohammad Gh. Mohammad, Kewal K. Saluja
2008Industry Standards from Accellera.Shrenik Mehta
2008A Galois Field Based Logic Synthesis Approach with Testability.Jimson Mathew, Hafizur Rahaman, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan
2008Design of Reversible Finite Field Arithmetic Circuits with Error Detection.Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan
2008Single Error Correcting Finite Field Multipliers Over GF(2m).Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan
2008Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation.Yuanlin Lu, Vishwani D. Agrawal
2008Stall Power Reduction in Pipelined Architecture Processors.Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi
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