| 2008 | DFM / DFT / SiliconDebug / Diagnosis. | Srikanth Venkataraman, Nagesh Tamarapalli |
| 2008 | A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. | Hari Vijay Venkatanarayanan, Michael L. Bushnell |
| 2008 | A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. | Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas |
| 2008 | Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation. | Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen |
| 2008 | Multimedia Tools and Architectures for Hardware/Software Co-Simulation of Reconfigurable Systems. | Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel, Manuel Almeida |
| 2008 | Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in Hardware. | Iouliia Skliarova, Valery Sklyarov |
| 2008 | A Module Checking Based Converter Synthesis Approach for SoCs. | Roopak Sinha, Partha S. Roop, Samik Basu |
| 2008 | Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design. | Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar |
| 2008 | Scan Delay Testing of Nanometer SoCs. | Adit D. Singh |
| 2008 | Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture. | Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rtteler, Niraj K. Jha |
| 2008 | Simulation Acceleration with HW Re-Compilation Avoidance. | Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang |
| 2008 | MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method. | Hao Shen, Frdric Ptrot |
| 2008 | Concurrent Multi-Dimensional Adaptation for Low-Power Operation in Wireless Devices. | Rajarajan Senguttuvan, Shreyas Sen, Abhijit Chatterjee |
| 2008 | An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations. | Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi |
| 2008 | A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. | Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri |
| 2008 | Dynamic Aggregation of Virtual Addresses in TLB Using TCAM Cells. | Rupak Samanta, Jason Surprise, Rabi N. Mahapatra |
| 2008 | NBTI Degradation: A Problem or a Scare? | Kewal K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang |
| 2008 | A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier. | Sounak Roy, Swapna Banerjee |
| 2008 | Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding. | Shahid Rizwan |
| 2008 | Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier. | Chester Rebeiro, Debdeep Mukhopadhyay |
| 2008 | A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor. | Biswajit Ray, Santanu Mahapatra |
| 2008 | Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design. | Srividhya Rammohan, Vijay Sundaresan, Ranga Vemuri |
| 2008 | An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators. | Jaime Ramrez-Angulo, Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Sri Raga Sudha Garimella, Antonio J. Lpez-Martn, Ramn Gonzlez Carvajal |
| 2008 | VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair. | S. Ramasamy, B. Venkataramani, K. Anbugeetha |
| 2008 | A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores. | Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron |