| 2003 | Small Signal Characteristics of Thin Film Single Halo SOI MOSFET for Mixed Mode Applications. | Najeeb-ud-Din Hakim, V. Ramgopal Rao, J. Vasi |
| 2003 | SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations. | Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau |
| 2003 | Resource Allocation and Binding Approach for Low Leakage Power. | Chandramouli Gopalakrishnan, Srinivas Katkoori |
| 2003 | Comparison of Bistable Circuits Based on Resonant-Tunneling Diodes. | Alejandro F. Gonzlez, Pinaki Mazumder |
| 2003 | VLSI Implementation of Online Digital Watermarking Technique with Difference Encoding for 8-Bit Gray Scale Images. | Annajirao Garimella, M. V. V. Satyanarayana, R. Satish Kumar, P. S. Murugesh, U. C. Niranjan |
| 2003 | Personal and Portable: The Evolving Definition. | Gene A. Frantz |
| 2003 | SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs. | Petros Drineas, Yiorgos Makris |
| 2003 | A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime. | Abhisek Dixit, V. Ramgopal Rao |
| 2003 | The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance. | Li Ding, Pinaki Mazumder |
| 2003 | Analyzing Soft Errors in Leakage Optimized SRAM Design. | Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin |
| 2003 | Design Of A Universal BIST (UBIST) Structure. | Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri |
| 2003 | Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology. | Koushik K. Das, Richard B. Brown |
| 2003 | A Memory Efficient 3-D DWT Architecture. | Bipul Das, Swapna Banerjee |
| 2003 | Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy. | Zhibin Dai, Dilip K. Banerji |
| 2003 | On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. | Geun Rae Cho, Tom Chen |
| 2003 | An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits. | Jong-Sheng Cherng, Sao-Jie Chen |
| 2003 | Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips. | Santanu Chattopadhyay, K. Sudarsana Reddy |
| 2003 | Genetic Algorithm based Approach for Low Power Combinational Circuit Testing. | Santanu Chattopadhyay, Naveen Choudhary |
| 2003 | Specification and Design of Multi-Million Gate SOCs. | Ramesh Chandra, Preeti Ranjan Panda, Jrg Henkel, Sri Parameswaran, Loganath Ramachandran |
| 2003 | A Path Sensitization Technique for Testing of Switched Capacitor Circuits. | Sounil Biswas, Baquer Mazhari |
| 2003 | Interfacing Cores with On-chip Packet-Switched Networks. | Praveen Bhojwani, Rabi N. Mahapatra |
| 2003 | Low-Energy BIST Design for Scan-based Logic Circuits. | Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang |
| 2003 | Interface Design Techniques for Single-Chip Systems. | Robert H. Bell Jr., Lizy Kurian John |
| 2003 | A Method to Estimate Slew and Delay in Coupled Digital Circuits. | Shabbir H. Batterywala, Narendra V. Shenoy |
| 2003 | High Level Synthesis from Sim-nML Processor Models. | Souvik Basu, Rajat Moona |