| 2010 | Board-level fault diagnosis using Bayesian inference. | Zhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty |
| 2010 | Multitone digital signal based test for RF receivers. | Mohamad A. Zeidan, Aritra Banerjee, Ranjit Gharpurey, Jacob A. Abraham |
| 2010 | Scalable and accurate estimation of probabilistic behavior in sequential circuits. | Chien-Chih Yu, John P. Hayes |
| 2010 | Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. | Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara |
| 2010 | Application of signal and noise theory to digital VLSI testing. | Nitin Yogi, Vishwani D. Agrawal |
| 2010 | Impact of multiple input switching on delay test under process variation. | Sean H. Wu, Sreejit Chakravarty, Li-C. Wang |
| 2010 | Fabrication and testing of large-area flexible electronics for displays and sensor arrays. | William S. Wong |
| 2010 | CSER: BISER-based concurrent soft-error resilience. | Laung-Terng Wang, Nur A. Touba, Zhigang Jiang, Shianling Wu, Jiun-Lang Huang, James Chien-Mo Li |
| 2010 | Low-sensitivity to process variations aging sensor for automotive safety-critical applications. | Julio Csar Vzquez, Vctor H. Champac, Adriel Ziesemer, Ricardo Reis, Isabel Maria Cacho Teixeira, Marcelino B. Santos, Joo Paulo Teixeira |
| 2010 | Easing the verification bottleneck using high level synthesis. | D. Varma, D. Mackay, P. Thiruchelvam |
| 2010 | Path clustering for adaptive test. | Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato |
| 2010 | On-the-fly variation tolerant mapping in crossbar nano-architectures. | Cihan Tunc, Mehdi Baradaran Tahoori |
| 2010 | Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost. | Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li |
| 2010 | Industrial practices of test cost reduction: Perspective, current design practices. | Sarveswara Tammali |
| 2010 | Innovative practices session 3C: Industrial practices of test cost reduction techniques: Impact and design tradeoffs. | Sarveswara Tammali |
| 2010 | Evaluating yield and testing impact of sub-wavelength lithography. | Wing Chiu Tam, R. D. (Shawn) Blanton, Wojciech Maly |
| 2010 | Special session 12A: Panel adaptive analog test: Feasibility and opportunities ahead. | Haralampos-G. D. Stratigopoulos |
| 2010 | Special session 8A: TTTC 2010 E. J. McCluskey Best Doctoral Thesis Award. | Haralampos-G. D. Stratigopoulos |
| 2010 | Special session 4C: Thesis research poster session. | Haralampos-G. D. Stratigopoulos |
| 2010 | Special session 8C: Panel EDA for analog DFT/ATPG - will SoC cost pressures make this a reality? | Arani Sinha |
| 2010 | An output compression scheme for handling X-states from over-clocked delay tests. | Adit D. Singh, Chao Han, Xi Qian |
| 2010 | Too many faults, too little time on creating test sets for enhanced detection of highly critical faults and defects. | Yiwen Shi, Wan-Chan Hu, Jennifer Dworak |
| 2010 | Modeling yield, cost, and quality of an NoC with uniformly and non-uniformly distributed redundancy. | Saeed Shamshiri, Kwang-Ting Cheng |
| 2010 | A generic low power scan chain wrapper for designs using scan compression. | Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji |
| 2010 | Innovative practices session 7C: Verification and testing challenges in high-level synthesis. | Sandip Ray, Jayanta Bhadra |