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IEEE VLSI Test Symposium

VTS

National

CORE rank

CORE rank (raw)

National/Regional

Fields of research

Computer Systems Engineering

Papers indexed

2,208

1991–2026

Papers per year

199189 peak2026

VTS papers

2,208 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2011Prediction of compression bound and optimization of compression architecture for linear decompression-based schemes.Jia Li, Yu Huang, Dong Xiang
2011Memory-based embedded digital ATE.Dongsoo Lee, Sang Phill Park, Ashish Goel, Kaushik Roy
2011Advanced methods for leveraging new test standards.Mike Laisne
2011Apprentice - VTS edition: Season 4.Kee Sup Kim, Rob Roy
2011Levelized low cost delay test compaction considering IR-drop induced power supply noise.Zhongwei Jiang, Zheng Wang, Jing Wang, D. M. H. Walker
2011Efficient and product-representative timing model validation.Eun Jung Jang, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham
2011A built-in self-test scheme for the post-bond test of TSVs in 3D ICs.Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
2011A diagnosis testbench of analog IP cores against on-chip environmental disturbances.Takushi Hashida, Yuuki Araga, Makoto Nagata
2011Design for Bit Error Rate estimation of high speed serial links.Ujjwal Guin, Chen-Huan Chiang
2011Impact of the application activity on intermittent faults in embedded systems.Julien Guilhemsang, Olivier Hron, Nicolas Ventroux, Olivier Goncalves, Alain Giulieri
2011Programmable extended SEC-DED codes for memory errors.Valentin Gherman, Samuel Evain, Fabrice Auzanneau, Yannick Bonhomme
2011Invited paper: Yin and Yang of embedded sensors for post-scaling-era.Anne Gattiker
2011Special session 4A: New topics parametric yield and reliability of 3D integrated circuits: New challenges and solutions.Siddharth Garg, Diana Marculescu
2011An analytical method for estimating SET propagation.Sreenivas Gangadhar, Spyros Tragoudas
2011Designing a fast and adaptive error correction scheme for increasing the lifetime of phase change memories.Rudrajit Datta, Nur A. Touba
2011A scan cell architecture for inter-clock at-speed delay testing.Kyoung Youn Cho, Rajagopalan Srinivasan
2011Low Coverage Analysis using dynamic un-testability debug in ATPG.Kameshwar Chandrasekar, Surendra Bommu, Sanjay Sengupta
2011Harmony Widget for X-free scan testing.Dilip K. Bhavsar
2011Efficient trace data compression using statically selected dictionary.Kanad Basu, Prabhat Mishra
2011Automatic test stimulus generation for accurate diagnosis of RF systems using transient response signatures.Aritra Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee
2011Enhancing online error detection through area-efficient multi-site implications.Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal
2011Revival of partial scan: Test cube analysis driven conversion of flip-flops.Nader Alawadhi, Ozgur Sinanoglu
2011An efficient test data reduction technique through dynamic pattern mixing across multiple fault models.Srinivasulu Alampally, R. T. Venkatesh, Priyadharshini Shanmugasundaram, Rubin A. Parekhji, Vishwani D. Agrawal
2010Low-power test planning for arbitrary at-speed delay-test clock schemes.Christian G. Zoellin, Hans-Joachim Wunderlich
2010Pin-count-aware online testing of digital microfluidic biochips.Yang Zhao, Krishnendu Chakrabarty
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Comparable venues

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