| 2011 | Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. | Suraj Sindia, Vishwani D. Agrawal, Virendra Singh |
| 2011 | Training-based forming process for RRAM yield improvement. | Hsiu-Chuan Shih, Ching-Yi Chen, Cheng-Wen Wu, Chih-He Lin, Shyh-Shyuan Sheu |
| 2011 | Dynamic scan clock control for test time reduction maintaining peak power limit. | Priyadharshini Shanmugasundaram, Vishwani D. Agrawal |
| 2011 | Test and characterization of high-speed circuits. | Saghir A. Shaikh |
| 2011 | Leakage power profiling and leakage power reduction using DFT hardware. | Rajamani Sethuram, Karim Arabi, Mohamed H. Abu-Rahma |
| 2011 | Special session: Multifaceted approaches for field reliability. | Yasuo Sato |
| 2011 | Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips. | Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu |
| 2011 | Expedited response compaction for scan power reduction. | Samah Mohamed Saeed, Ozgur Sinanoglu |
| 2011 | Security-aware SoC test access mechanisms. | Kurt Rosenfeld, Ramesh Karri |
| 2011 | Design and analysis of ring oscillator based Design-for-Trust technique. | Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu, Ramesh Karri |
| 2011 | On clustering of undetectable transition faults in standard-scan circuits. | Irith Pomeranz |
| 2011 | Static test compaction for delay fault test sets consisting of broadside and skewed-load tests. | Irith Pomeranz |
| 2011 | Case Study: Efficient SDD test generation for very large integrated circuits. | Ke Peng, Fang Bao, Geoff Shofner, LeRoy Winemberg, Mohammad Tehranipoor |
| 2011 | A unified test architecture for on-line and off-line delay fault detections. | Songwei Pei, Huawei Li, Xiaowei Li |
| 2011 | Scan chain and power delivery network synthesis for pre-bond test of 3D ICs. | Shreepad Panth, Sung Kyu Lim |
| 2011 | Practical signal processing at mixed signal test venues - Trend removal, noise reduction, wideband signal capturing -. | Hideo Okawara |
| 2011 | A distributed AXI-based platform for post-silicon validation. | Mohammad Hossein Neishaburi, Zeljko Zilic |
| 2011 | The buck stops with wafer test: Dream or reality? | Suriyaprakash Natarajan, Arani Sinha |
| 2011 | Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation. | Prakash Narayanan, Rajesh Mittal, Sumanth Poddutur, Vivek Singhal, Puneet Sabbarwal |
| 2011 | A new methodology for realistic open defect detection probability evaluation under process variations. | Jess Moreno, Vctor H. Champac, Michel Renovell |
| 2011 | Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors. | Celestino V. Martins, Jorge Semio, Julio Csar Vzquez, Vctor H. Champac, Marcelino B. Santos, Isabel C. Teixeira, Joo Paulo Teixeira |
| 2011 | Exponent monitoring for low-cost concurrent error detection in FPU control logic. | Michail Maniatakos, Yiorgos Makris, Prabhakar Kudva, Bruce M. Fleischer |
| 2011 | A Novel mechanism for speed characterization during delay test. | Amitava Majumdar, Arani Sinha, Nehal Patel, Ramamurthy Setty, Yan Dong, Shu-Hsuan Chou |
| 2011 | Low-cost diagnostic pattern generation and evaluation procedures for noise-related failures. | Junxia Ma, Nisar Ahmed, Mohammad Tehranipoor |
| 2011 | Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs. | W.-A. Lin, C.-C. Lee, J.-L. Huang |