| 1995 | An apparatus for pseudo-deterministic testing. | Shridhar K. Mukund, Edward J. McCluskey, T. R. N. Rao |
| 1995 | Arithmetic built-in self test for high-level synthesis. | Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer |
| 1995 | The use of IDDQ testing in low stuck-at coverage situations. | Peter C. Maxwell |
| 1995 | Checking experiments to test latches. | Samy Makar, Edward J. McCluskey |
| 1995 | CURRENT: a test generation system for I | Udo Mahlstedt, Jrgen Alt, Matthias Heinitz |
| 1995 | High level fault modeling of asynchronous circuits. | Ding Lu, Carol Q. Tong |
| 1995 | Identifying sequentially untestable faults using illegal states. | David E. Long, Mahesh A. Iyer, Miron Abramovici |
| 1995 | Diagnosis of interconnects and FPICs using a structured walking-1 approach. | Tong Liu, Fabrizio Lombardi, Jos Salinas |
| 1995 | Switch-level modeling of transistor-level stuck-at faults. | Peter Lidn, Peter Dahlgren |
| 1995 | Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits. | Samir Lejmi, Bozena Kaminska, Bechir Ayari |
| 1995 | An optimized testable architecture for finite state machines. | Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja |
| 1995 | Generation of high quality tests for functional sensitizable paths. | Angela Krstic, Kwang-Ting Cheng |
| 1995 | Compact test sets for industrial circuits. | M. H. Konijnenburg, J. Th. van der Linden, Ad J. van de Goor |
| 1995 | A partial scan methodology for testing self-timed circuits. | Ajay Khoche, Erik Brunvand |
| 1995 | Frequency-based BIST for analog circuit testin. | Khaled Saab, Bozena Kaminska, Bernard Courtois, Marcelo Lubaszewski |
| 1995 | Synthesis of locally exhaustive test pattern generators. | Gnter Kemnitz |
| 1995 | Multifault testability of delay-testable circuits. | Wuudiann Ke, Premachandran R. Menon |
| 1995 | A scheduling problem in test generation. | Tomoo Inoue, Hironori Maeda, Hideo Fujiwara |
| 1995 | A distance reduction approach to design for testability. | Frank F. Hsu, Janak H. Patel |
| 1995 | On the application of local circuit transformations with special emphasis on path delay fault testability. | Harry Hengster, Rolf Drechsler, Bernd Becker |
| 1995 | High-level test generation using physically-induced faults. | Mark C. Hansen, John P. Hayes |
| 1995 | A tool for automatic generation of self-checking data paths. | B. Hamdi, Hakim Bederr, Michael Nicolaidis |
| 1995 | RT level testability-driven partitioning. | Xinli Gu |
| 1995 | Testing combinational iterative logic arrays for realistic faults. | Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis |
| 1995 | Diagnostic of path and gate delay faults in non-scan sequential circuits. | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez |