| 1993 | Analysis of redundant structures in combinational circuits. | Eugeni Isern, Joan Figueras |
| 1993 | Sensitivity analysis of a radiation immune CMOS logic family under defect conditions. | Erik H. Ingermann, James F. Frenzel |
| 1993 | Functional verification and simulation of FSM networks. | Zafar Hasan, Maciej J. Ciesielski |
| 1993 | Testability of one dimensional ILAs under multiple faults. | Murali M. R. Gala, Karan L. Watson, Don E. Ross |
| 1993 | Estimation of reject ratio in testing of combinatorial circuits. | Dinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly |
| 1993 | Physical design for testability for bridges in CMOS circuits. | F. Joel Ferguson |
| 1993 | On the maximum value of aliasing probabilities for single input signature registers. | Shou-ping Feng, Toru Fujiwara, Tadao Kasami, Kazuhiko Iwasaki |
| 1993 | Time and space correlated errors in signature analysis. | Geetani Edirisooriya, Samantha Edirisooriya, John P. Robinson |
| 1993 | A new built-in self-test method based on prestored testing. | Geetani Edirisooriya, Samantha Edirisooriya, John P. Robinson |
| 1993 | Pattern generator card, emulation, and debug. | Stephen M. Dunn, D. G. Balazich, Lawrence K. Lange, Charlotte C. Montillo |
| 1993 | LFSROM an algorithm for automatic design synthesis of hardware test pattern generator. | Christian Dufaza, Cyril Chevalier, Lew Fock Chong Lew Yan Voon |
| 1993 | On CMOS bridge fault modeling and test pattern evaluation. | Chennian Di, Jochen A. G. Jess |
| 1993 | Fault injection scan design for enhanced VLSI design verification. | Savio N. Chau |
| 1993 | Simulation and generation of I | Sreejit Chakravarty, Paul J. Thadikaran |
| 1993 | Aliasing-free error detection (ALFRED). | Krishnendu Chakrabarty, John P. Hayes |
| 1993 | Input and output encoding techniques for on-line error detection in combinational logic circuits. | Fadi Y. Busaba, Parag K. Lala |
| 1993 | A neural inverse function for automatic test pattern generation using strictly digital neural networks. | Masatoshi Arai, Tohru Nakagawa, Hajime Kitagawa |
| 1993 | Simulation of non-classical faults on the gate level-fault modeling. | Jrgen Alt, Udo Mahlstedt |
| 1993 | Concurrent error correction in iterative circuits by recomputing with partitioning and voting. | Hussain Al-Asaad, Edward C. Czeck |
| 1993 | Partial scan testing with single clock control. | Vishwani D. Agrawal, Tapan J. Chakraborty |
| 1993 | Degrading fault model for WSI interconnection lines. | Hussam Y. Abujbara, Sami A. Al-Arian |
| 1993 | On the design for testability of sequential circuits. | Xiao Sun, Fabrizio Lombardi |
| 1992 | HLSIM-a new hierarchical logic simulator in APL. | David A. Zein, Oliver P. Engel, Gary S. Ditlow |
| 1992 | Algorithms for the design verification of bipolar array chips. | David A. Zein, Oliver P. Engel, Gary S. Ditlow |
| 1992 | Multiple redundancy removal during test generation and synthesis. | David M. Wu, Robert M. Swanson |