| 2025 | CVPR | SimCache: Similarity Caching for Efficient VLM-based Scene Understanding. | Surya Selvam, Ravi K. Rajendran, Murugan Sankaradas, Anand Raghunathan, Srimat T. Chakradhar |
| 2025 | DAC | 3D-CIMlet: A Chiplet Co-Design Framework for Heterogeneous In-Memory Acceleration of Edge LLM Inference and Continual Learning. | Shuting Du, Luqi Zheng, Aradhana Mohan Parvathy, Feifan Xie, Tiwei Wei, Anand Raghunathan, Haitong Li |
| 2025 | ISLPED | ML-Power: Machine Learning based Power Estimation for SoCs. | Sujay Pandit, Sujit Dey, Anand Raghunathan |
| 2024 | DAC | Ev-Edge: Efficient Execution of Event-based Vision Algorithms on Commodity Edge Platforms. | Shrihari Sridharan, Surya Selvam, Kaushik Roy, Anand Raghunathan |
| 2023 | EMNLP | TokenDrop + BucketSampler: Towards Efficient Padding-free Fine-tuning of Language Models. | Amrit Nagarajan, Anand Raghunathan |
| 2022 | DAC | Efficiency attacks on spiking neural networks. | Sarada Krithivasan, Sanchari Sen, Nitin Rathi, Kaushik Roy, Anand Raghunathan |
| 2022 | DAC | Efficient ensembles of graph neural networks. | Amrit Nagarajan, Jacob R. Stevens, Anand Raghunathan |
| 2022 | DAC | A cross-layer approach to cognitive computing: invited. | Gobinda Saha, Cheng Wang, Anand Raghunathan, Kaushik Roy |
| 2022 | ICCAD | Approximate Computing and the Efficient Machine Learning Expedition. | Jrg Henkel, Hai Li, Anand Raghunathan, Mehdi B. Tahoori, Swagath Venkataramani, Xiaoxuan Yang, Georgios Zervakis |
| 2022 | ICCAD | Seprox: Sequence-Based Approximations for Compressing Ultra-Low Precision Deep Neural Networks. | Aradhana Mohan Parvathy, Sarada Krithivasan, Sanchari Sen, Anand Raghunathan |
| 2022 | IJCNN | AxFormer: Accuracy-driven Approximation of Transformers for Faster, Smaller and more Accurate NLP Models. | Amrit Nagarajan, Sanchari Sen, Jacob R. Stevens, Anand Raghunathan |
| 2022 | ISLPED | Energy Efficient Cache Design with Piezoelectric FETs. | Reena Elangovan, Ashish Ranjan, Niharika Thakuria, Sumeet Kumar Gupta, Anand Raghunathan |
| 2022 | ISLPED | Layerwise Disaggregated Evaluation of Spiking Neural Networks. | Abinand Nallathambi, Sanchari Sen, Anand Raghunathan, Nitin Chandrachoodan |
| 2021 | DAC | GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks. | Jacob R. Stevens, Dipankar Das, Sasikanth Avancha, Bharat Kaul, Anand Raghunathan |
| 2021 | DAC | Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. | Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan |
| 2021 | DATE | Value Similarity Extensions for Approximate Computing in General-Purpose Processors. | Younghoon Kim, Swagath Venkataramani, Sanchari Sen, Anand Raghunathan |
| 2021 | ISLPED | Efficacy of Pruning in Ultra-Low Precision DNNs. | Sanchari Sen, Swagath Venkataramani, Anand Raghunathan |
| 2020 | DATE | Emerging Neural Workloads and Their Impact on Hardware. | David Brooks, Martin M. Frank, Tayfun Gokmen, Udit Gupta, Xiaobo Sharon Hu, Shubham Jain, Ann Franchesca Laguna, Michael T. Niemier, Ian O'Connor, Anand Raghunathan, Ashish Ranjan, Dayane Reis, Jacob R. Stevens, Carole-Jean Wu, Xunzhao Yin |
| 2020 | DATE | Sparsity-Aware Caches to Accelerate Deep Neural Networks. | Vinod Ganesan, Sanchari Sen, Pratyush Kumar, Neel Gala, Kamakoti Veezhinathan, Anand Raghunathan |
| 2020 | DATE | Communication-efficient View-Pooling for Distributed Multi-View Neural Networks. | Manik Singhal, Vijay Raghunathan, Anand Raghunathan |
| 2020 | DATE | Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks. | Sandeep Krishna Thirumala, Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan |
| 2020 | ICLR | EMPIR: Ensembles of Mixed Precision Deep Networks for Increased Robustness Against Adversarial Attacks. | Sanchari Sen, Balaraman Ravindran, Anand Raghunathan |
| 2020 | IJCNN | Pruning Filters while Training for Efficiently Optimizing Deep Learning Networks. | Sourjya Roy, Priyadarshini Panda, Gopalakrishnan Srinivasan, Anand Raghunathan |
| 2019 | COMAD | Pack and Detect: Fast Object Detection in Videos Using Region-of-Interest Packing. | Athindran Ramesh Kumar, Balaraman Ravindran, Anand Raghunathan |
| 2019 | DAC | X-MANN: A Crossbar based Architecture for Memory Augmented Neural Networks. | Ashish Ranjan, Shubham Jain, Jacob R. Stevens, Dipankar Das, Bharat Kaul, Anand Raghunathan |
| 2019 | DATE | Data Subsetting: A Data-Centric Approach to Approximate Computing. | Younghoon Kim, Swagath Venkataramani, Nitin Chandrachoodan, Anand Raghunathan |
| 2019 | ISLPED | Dynamic Spike Bundling for Energy-Efficient Spiking Neural Networks. | Sarada Krithivasan, Sanchari Sen, Swagath Venkataramani, Anand Raghunathan |
| 2019 | ISLPED | Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation. | Sandeep Krishna Thirumala, Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta |
| 2019 | MICRO | Manna: An Accelerator for Memory-Augmented Neural Networks. | Jacob R. Stevens, Ashish Ranjan, Dipankar Das, Bharat Kaul, Anand Raghunathan |
| 2018 | DATE | Computing-in-memory with spintronics. | Shubham Jain, Sachin S. Sapatnekar, Jianping Wang, Kaushik Roy, Anand Raghunathan |
| 2018 | DATE | ACCLIB: Accelerators as libraries. | Jacob R. Stevens, Yue Du, Vivek Kozhikkott, Anand Raghunathan |
| 2018 | ICCAD | AxBA: an approximate bus architecture framework. | Jacob R. Stevens, Ashish Ranjan, Anand Raghunathan |
| 2018 | ICCD | SYNCVIBE: Fast and Secure Device Pairing through Physical Vibration on Commodity Smartphones. | Kyuin Lee, Vijay Raghunathan, Anand Raghunathan, Younghyun Kim |
| 2017 | DAC | A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. | Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami |
| 2017 | DATE | STAxCache: An approximate, energy efficient STT-MRAM cache. | Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan |
| 2017 | DATE | Approximate computing for spiking neural networks. | Sanchari Sen, Swagath Venkataramani, Anand Raghunathan |
| 2017 | ISCA | ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks. | Swagath Venkataramani, Ashish Ranjan, Subarno Banerjee, Dipankar Das, Sasikanth Avancha, Ashok Jagannathan, Ajaya Durg, Dheemanth Nagaraj, Bharat Kaul, Pradeep Dubey, Anand Raghunathan |
| 2017 | ISLPED | AXSERBUS: A quality-configurable approximate serial bus for energy-efficient sensing. | Younghyun Kim, Setareh Behroozi, Vijay Raghunathan, Anand Raghunathan |
| 2017 | ISLPED | Approximate memory compression for energy-efficiency. | Ashish Ranjan, Arnab Raha, Vijay Raghunathan, Anand Raghunathan |
| 2017 | ISLPED | A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks. | Arnab Roy, Swagath Venkataramani, Neel Gala, Sanchari Sen, Kamakoti Veezhinathan, Anand Raghunathan |
| 2017 | PPoPP | Model-based Iterative CT Image Reconstruction on GPUs. | Amit Sabne, Xiao Wang, Sherman J. Kisner, Charles A. Bouman, Anand Raghunathan, Samuel P. Midkiff |
| 2016 | ASPDAC | Efficient embedded learning for IoT devices. | Swagath Venkataramani, Kaushik Roy, Anand Raghunathan |
| 2016 | DAC | Designing approximate circuits using clock overgating. | Younghoon Kim, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan |
| 2016 | DAC | Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems. | Priyadarshini Panda, Abhronil Sengupta, Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy |
| 2016 | DATE | Approximation through logic isolation for the design of quality configurable circuits. | Shubham Jain, Swagath Venkataramani, Anand Raghunathan |
| 2016 | DATE | Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing. | Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy |
| 2016 | ISLPED | STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection. | Neel Gala, Swagath Venkataramani, Anand Raghunathan, V. Kamakoti |
| 2016 | PPoPP | High performance model based image reconstruction. | Xiao Wang, Amit Sabne, Sherman J. Kisner, Anand Raghunathan, Charles A. Bouman, Samuel P. Midkiff |
| 2016 | VLSID | Neuromorphic Computing Enabled by Spin-Transfer Torque Devices. | Abhronil Sengupta, Priyadarshini Panda, Anand Raghunathan, Kaushik Roy |
| 2016 | VLSID | Approximate Computing. | Swagath Venkataramani, Kaushik Roy, Anand Raghunathan |
| 2015 | DAC | Vibration-based secure side channel for medical devices. | Younghyun Kim, Woo Suk Lee, Vijay Raghunathan, Niraj K. Jha, Anand Raghunathan |
| 2015 | DAC | Approximate storage for energy efficient spintronic memories. | Ashish Ranjan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan |
| 2015 | DAC | Approximate computing and the quest for computing efficiency. | Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan |
| 2015 | DAC | Scalable-effort classifiers for energy-efficient machine learning. | Swagath Venkataramani, Anand Raghunathan, Jie Liu, Mohammed Shoaib |
| 2015 | DATE | Asymmetric underlapped FinFET based robust SRAM design at 7nm node. | A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy |
| 2015 | DATE | Quality configurable reduce-and-rank for energy efficient approximate computing. | Arnab Raha, Swagath Venkataramani, Vijay Raghunathan, Anand Raghunathan |
| 2015 | DATE | DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s. | Ashish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay S. Pai, Kaushik Roy, Anand Raghunathan |
| 2015 | DATE | Computing approximately, and efficiently. | Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan |
| 2015 | DATE | Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing. | Rangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan |
| 2014 | DAC | Variation Aware Cache Partitioning for Multithreaded Programs. | Vivek Joy Kozhikkottu, Abhisek Pan, Vijay S. Pai, Sujit Dey, Anand Raghunathan |
| 2014 | DATE | ASLAN: Synthesis of approximate sequential circuits. | Ashish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan |
| 2014 | ISCA | STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies. | Rangharajan Venkatesan, Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan |
| 2014 | ISLPED | StoRM: a stochastic recognition and mining processor. | Vinay K. Chippa, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan |
| 2014 | ISLPED | Variation tolerant design of a vector processor for recognition, mining and synthesis. | Vivek Joy Kozhikkottu, Swagath Venkataramani, Sujit Dey, Anand Raghunathan |
| 2014 | ISLPED | SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing. | Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan |
| 2014 | ISLPED | AxNN: energy-efficient neuromorphic systems using approximate computing. | Swagath Venkataramani, Ashish Ranjan, Kaushik Roy, Anand Raghunathan |
| 2014 | USENIX | ShuffleWatcher: Shuffle-aware Scheduling in Multi-tenant MapReduce Clusters. | Faraz Ahmad, Srimat T. Chakradhar, Anand Raghunathan, T. N. Vijaykumar |
| 2013 | ACSSC | Approximate computing: An integrated hardware approach. | Vinay K. Chippa, Swagath Venkataramani, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan |
| 2013 | DAC | Analysis and characterization of inherent application resilience for approximate computing. | Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan |
| 2013 | DAC | Relax-and-retime: a methodology for energy-efficient recovery based design. | Shankar Ganesh Ramasubramanian, Swagath Venkataramani, Adithya Parandhaman, Anand Raghunathan |
| 2013 | DAC | Towards trustworthy medical devices and body area networks. | Meng Zhang, Anand Raghunathan, Niraj K. Jha |
| 2013 | DATE | Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits. | Swagath Venkataramani, Kaushik Roy, Anand Raghunathan |
| 2013 | DATE | DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes. | Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan |
| 2013 | IOLTS | Approximate computing: Energy-efficient computing with good-enough results. | Anand Raghunathan, Kaushik Roy |
| 2013 | ISLPED | Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches. | Mrigank Sharad, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy |
| 2013 | MICRO | Quality programmable vector processors for approximate computing. | Swagath Venkataramani, Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan |
| 2013 | VLSID | Localized Heating for Building Energy Efficiency. | Jun Wei Chuah, Chunxiao Li, Niraj K. Jha, Anand Raghunathan |
| 2013 | VLSID | Emerging Frontiers in Embedded Security. | Mehran Mozaffari Kermani, Meng Zhang, Anand Raghunathan, Niraj K. Jha |
| 2013 | VLSID | Energy-efficient and Secure Sensor Data Transmission Using Encompression. | Meng Zhang, Mehran Mozaffari Kermani, Anand Raghunathan, Niraj K. Jha |
| 2012 | ASPLOS | Tarazu: optimizing MapReduce on heterogeneous clusters. | Faraz Ahmad, Srimat T. Chakradhar, Anand Raghunathan, T. N. Vijaykumar |
| 2012 | CLUSTER | PIC: Partitioned Iterative Convergence for Clusters. | Reza Farivar, Anand Raghunathan, Srimat T. Chakradhar, Harshit Kharbanda, Roy H. Campbell |
| 2012 | DAC | Recovery-based design for variation-tolerant SoCs. | Vivek Joy Kozhikkottu, Sujit Dey, Anand Raghunathan |
| 2012 | DAC | Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture. | Sang Phill Park, Sumeet Kumar Gupta, Niladri Narayan Mojumder, Anand Raghunathan, Kaushik Roy |
| 2012 | DAC | SALSA: systematic logic synthesis of approximate circuits. | Swagath Venkataramani, Amit Sabne, Vivek Joy Kozhikkottu, Kaushik Roy, Anand Raghunathan |
| 2012 | DSD | On Modeling and Evaluation of Logic Circuits under Timing Variations. | Mehdi Dehbashi, Grschwin Fey, Kaushik Roy, Anand Raghunathan |
| 2012 | ETS | Functional analysis of circuits under timing variations. | Mehdi Dehbashi, Grschwin Fey, Kaushik Roy, Anand Raghunathan |
| 2012 | ISLPED | TapeCache: a high density, energy efficient cache based on domain wall memory. | Rangharajan Venkatesan, Vivek Joy Kozhikkottu, Charles Augustine, Arijit Raychowdhury, Kaushik Roy, Anand Raghunathan |
| 2012 | SC | Automatic generation of software pipelines for heterogeneous parallel systems. | Jacques A. Pienaar, Srimat T. Chakradhar, Anand Raghunathan |
| 2011 | DAC | Dynamic effort scaling: managing the quality-efficiency tradeoff. | Vinay K. Chippa, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar |
| 2011 | DATE | VESPA: Variability emulation for System-on-Chip performance analysis. | Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey |
| 2011 | DATE | Design of voltage-scalable meta-functions for approximate computing. | Debabrata Mohapatra, Vinay K. Chippa, Anand Raghunathan, Kaushik Roy |
| 2011 | ICCAD | MACACO: Modeling and analysis of circuits for approximate computing. | Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan |
| 2011 | ICS | MDR: performance model driven runtime for heterogeneous parallel platforms. | Jacques A. Pienaar, Anand Raghunathan, Srimat T. Chakradhar |
| 2011 | ISLPED | IMPACT: imprecise adders for low-power approximate computing. | Vaibhav Gupta, Debabrata Mohapatra, Sang Phill Park, Anand Raghunathan, Kaushik Roy |
| 2010 | ASPLOS | Best-effort semantic document search on GPUs. | Surendra Byna, Jiayuan Meng, Anand Raghunathan, Srimat T. Chakradhar, Srihari Cadambi |
| 2010 | DAC | Best-effort computing: re-thinking parallel software and hardware. | Srimat T. Chakradhar, Anand Raghunathan |
| 2010 | DAC | Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. | Vinay K. Chippa, Debabrata Mohapatra, Anand Raghunathan, Kaushik Roy, Srimat T. Chakradhar |
| 2010 | VLSID | Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components. | Kaushik Roy, Byunghoo Jung, Anand Raghunathan |
| 2010 | VTS | Special session 11B: Hot topic hardware security: Design, test and verification issues. | Swarup Bhunia, Anand Raghunathan |
| 2009 | DATE | An architecture for secure software defined radio. | Chunxiao Li, Anand Raghunathan, Niraj K. Jha |
| 2009 | VLSID | Coping with Variations through System-Level Design. | Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy |
| 2008 | DATE | Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor. | Janar Thoguluva, Anand Raghunathan, Srimat T. Chakradhar |
| 2008 | DIMVA | Dynamic Binary Instrumentation-Based Framework for Malware Defense. | Najwa Aaraj, Anand Raghunathan, Niraj K. Jha |
| 2007 | DAC | System-on-Chip Power Management Considering Leakage Power Variations. | Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2007 | DAC | Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation. | Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan |
| 2007 | DATE | Energy and execution time analysis of a software-based trusted platform module. | Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
| 2007 | VLSID | Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. | Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan |
| 2006 | DAC | Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. | Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar |
| 2006 | DAC | Systematic software-based self-test for pipelined processors. | Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi |
| 2006 | DATE | Architectures for efficient face authentication in embedded systems. | Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2006 | DATE | Satisfiability-based framework for enabling side-channel attacks on cryptographic software. | Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee |
| 2006 | DATE | Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. | Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2006 | DATE | Adaptive data placement in an embedded multiprocessor thread library. | Phillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan |
| 2006 | ISCC | Active Learning Driven Data Acquisition for Sensor Networks. | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
| 2006 | ISLPED | Considering process variations during system-level power analysis. | Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2006 | VLSID | Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. | Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha |
| 2006 | VLSID | Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2005 | CASES | SECA: security-enhanced communication architecture. | Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar |
| 2005 | DAC | Power emulation: a new paradigm for power estimation. | Joel Coburn, Srivaths Ravi, Anand Raghunathan |
| 2005 | DAC | Efficient fingerprint-based user authentication for embedded systems. | Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2005 | DAC | Hybrid simulation for embedded software energy estimation. | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
| 2005 | DAC | FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. | Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2005 | DATE | Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. | Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2005 | DATE | Hardware Accelerated Power Estimation. | Joel Coburn, Srivaths Ravi, Anand Raghunathan |
| 2005 | VLSID | Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. | Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar |
| 2005 | VLSID | Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. | Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar |
| 2005 | VLSID | Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2005 | SECON | Battery discharge characteristics of wireless sensor nodes: an experimental analysis. | Chulsung Park, Kanishka Lahiri, Anand Raghunathan |
| 2004 | DAC | Automated energy/performance macromodeling of embedded software. | Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha |
| 2004 | DAC | Security as a new dimension in embedded system design. | Srivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan |
| 2004 | ICCAD | High-level synthesis using computation-unit integrated memories. | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2004 | ICCAD | Power estimation for cycle-accurate functional descriptions of hardware. | Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2004 | VLSID | Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. | Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2004 | VLSID | Tamper Resistance Mechanisms for Secure, Embedded Systems. | Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar |
| 2004 | VLSID | Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization. | Weidong Wang, Anand Raghunathan, Niraj K. Jha |
| 2003 | DAC | A scalable software-based self-test methodology for programmable processors. | Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey |
| 2003 | DATE | Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. | Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi |
| 2003 | DATE | Energy Estimation for Extensible Processors. | Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2003 | DATE | Securing Mobile Appliances: New Challenges for the System Designer. | Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater |
| 2003 | DATE | Software Architectural Transformations: A New Approach to Low Energy Embedded Software. | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha |
| 2003 | ICCAD | Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2003 | ICCAD | A Scalable Application-Specific Processor Synthesis Methodology. | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2003 | ISLPED | Analyzing the energy consumption of security protocols. | Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2003 | VLSID | Embedding Security in Wireless Embedded Systems. | Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar |
| 2003 | VLSID | Efficient RTL Power Estimation for Large Designs. | Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar |
| 2003 | VLSID | High-level Synthesis of Multi-process Behavioral Descriptions. | Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey |
| 2002 | DAC | Communication architecture based power management for battery efficient system design. | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
| 2002 | DAC | System design methodologies for a wireless security processing platform. | Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass |
| 2002 | ICCAD | High-level synthesis of distributed logic-memory architectures. | Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2002 | ICCAD | Synthesis of custom processors based on extensible platforms. | Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha |
| 2002 | ICCD | Embedded Operating System Energy Analysis and Macro-Modeling. | Tat Kee Tan, Anand Raghunathan, Niraj K. Jha |
| 2002 | VLSID | Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. | Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi |
| 2002 | VLSID | High-Level Synthesis with SIMD Units. | Vijay Raghunathan, Anand Raghunathan, Mani B. Srivastava, Milos D. Ercegovac |
| 2002 | VLSID | Input Space Adaptive Embedded Software Synthesis. | Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha |
| 2002 | VTS | Innovations in Test Automation. | J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski |
| 2001 | DAC | LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. | Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana |
| 2001 | DAC | High-level Software Energy Macro-modeling. | Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha |
| 2001 | DAC | Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. | Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha |
| 2001 | ICCAD | Transient Power Management Through High Level Synthesis. | Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana |
| 2001 | VLSID | Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
| 2001 | VLSID | Battery Life Estimation of Mobile Embedded Systems. | Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla Fabiana Chiasserini, Anand Raghunathan |
| 2001 | VLSID | Accurate Power Macro-modeling Techniques for Complex RTL Circuits. | Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar |
| 2001 | VLSID | Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies. | Anand Raghunathan, Sujit Dey |
| 2000 | DAC | Power analysis of embedded operating systems. | Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha |
| 2000 | DAC | Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. | Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey |
| 2000 | DATE | Efficient Power Co-Estimation Techniques for System-on-Chip Design. | Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno |
| 2000 | ICCAD | Efficient Exploration of the SoC Communication Architecture Design Space. | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2000 | VLSID | Performance Analysis of Systems with Multi-Channel Communication Architectures. | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
| 1999 | DAC | Common-Case Computation: A High-Level Technique for Power and Performance Optimization. | Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey |
| 1999 | ICCAD | Fast performance analysis of bus-based system-on-chip communication architectures. | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 1999 | ICCD | Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. | Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya |
| 1999 | VLSID | Low Power Design Methodologies for Systems-on-Chips. | Kaushik Roy, Anand Raghunathan, Sujit Dey |
| 1998 | ASPDAC | Considering Testability during High-level Design (Embedded Tutorial). | Sujit Dey, Anand Raghunathan, Rabindra K. Roy |
| 1998 | DAC | Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha |
| 1998 | ICCAD | Verification of RTL generated from scheduled behavior in a high-level synthesis flow. | Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama |
| 1998 | ICCAD | Transforming control-flow intensive designs to facilitate power management. | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey |
| 1998 | VLSID | A Power Management Methodology for High-Level Synthesis. | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey |
| 1997 | DAC | Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
| 1997 | DAC | Power Management Techniques for Control-Flow Intensive Designs. | Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi |
| 1996 | DAC | Glitch Analysis and Reduction in Register Transfer Level. | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
| 1996 | ICCAD | A design for testability technique for RTL circuits using control/data flow extraction. | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
| 1996 | ICCAD | Register-transfer level estimation techniques for switching activity and power consumption. | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
| 1996 | ISLPED | Controller re-specification to minimize switching activity in controller/data path circuits. | Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi |
| 1996 | VLSID | Dynamic test Sequence compaction for Sequential Circuits. | Anand Raghunathan, Srimat T. Chakradhar |
| 1995 | ICCAD | Acceleration techniques for dynamic vector compaction. | Anand Raghunathan, Srimat T. Chakradhar |
| 1995 | ICCAD | An iterative improvement algorithm for low power data path synthesis. | Anand Raghunathan, Niraj K. Jha |
| 1995 | ICCD | Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. | Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha |
| 1995 | ISCAS | An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation. | Anand Raghunathan, Niraj K. Jha |
| 1995 | VLSID | Test generation for cyclic combinational circuits. | Anand Raghunathan, Pranav Ashar, Sharad Malik |
| 1994 | ICCD | Behavioral Synthesis for low Power. | Anand Raghunathan, Niraj K. Jha |