| 2014 | ICSEng | Rule Induction Based on Logic Synthesis Methods. | Grzegorz Borowik, Andrzej Krasniewski, Tadeusz Luba |
| 2012 | DDECS | Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching. | Jakub Korczyc, Andrzej Krasniewski |
| 2011 | ICSEng | A Tool for Trading-Off On-Line Error Detection Efficiency with Implementation Cost for Sequential Logic Implemented in FPGAs. | Grzegorz Borowik, Andrzej Krasniewski |
| 2008 | DDECS | Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs. | Andrzej Krasniewski |
| 2008 | DSD | Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs. | Andrzej Krasniewski |
| 2007 | DSD | Concurrent Error Detection for FSMs Designed for Implementation with Embedded Memory Blocks of FPGAs. | Andrzej Krasniewski |
| 2006 | DDECS | Low-Cost Concurrent Error Detection for FSMs Implemented Using Embedded Memory Blocks of FPGAs. | Andrzej Krasniewski |
| 2005 | IOLTS | A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory. | Andrzej Krasniewski |
| 2004 | FPL | Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory. | Andrzej Krasniewski |
| 2004 | IOLTS | Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks. | Andrzej Krasniewski |
| 2003 | FPL | Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices. | Andrzej Krasniewski |
| 2003 | IOLTS | Evaluation of the Quality of Testing Path Delay Faults under Restricted Input Assumption. | Andrzej Krasniewski |
| 2002 | FPL | On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs. | Andrzej Krasniewski |
| 2002 | FPL | Exploiting Reconfigurability for Effective Testing of Delay Faults in Sequential Subcircuits of LUT-based FPGAs. | Andrzej Krasniewski |
| 2001 | DSD | Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing. | Andrzej Krasniewski |
| 2001 | IOLTS | Testing FPGA Delay Faults in the System Environment is Very Different from "Ordinary" Delay Fault Testing. | Andrzej Krasniewski |
| 2000 | FPL | Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs. | Andrzej Krasniewski |
| 2000 | IOLTS | Self-Testing of FPGA Delay Faults in the System Environment. | Andrzej Krasniewski |
| 1996 | EDCC | Design of Dependable Hardware: What BIST is most Efficient? | Andrzej Krasniewski |
| 1994 | EDCC | Coverage of Delay Faults: When 13% and 99% Mean the Same. | Andrzej Krasniewski, Leszek B. Wronski |
| 1992 | ICCD | Design of Robust-Path-Delay-Fault-Testable Combinational Circuits by Boolean Space Expansion. | Xiaodong Xie, Alexander Albicki, Andrzej Krasniewski |
| 1992 | ITC | High Quality Testing of Embedded RAMs Using Circular Self-Test Path. | Andrzej Krasniewski, Slawomir Pilarski |
| 1991 | DAC | Logic Synthesis for Efficient Pseudoexhaustive Testability. | Andrzej Krasniewski |
| 1991 | ICCD | Random Testability of Redundant Circuits. | Andrzej Krasniewski, Alexander Albicki |
| 1991 | ITC | Can Redundancy Enhance Testability? | Andrzej Krasniewski |
| 1987 | DAC | Circular Self-Test Path: A Low-Cost BIST Technique. | Andrzej Krasniewski, Slawomir Pilarski |
| 1985 | DAC | Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications. | Andrzej Krasniewski, Alexander Albicki |
| 1985 | ITC | Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules. | Andrzej Krasniewski, Alexander Albicki |