Michel Renovell
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
70
Venues
9
Active years
1992–2019
Best venue rank
B
Where they publish
Papers
70 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2019 | ETS | B-open: A New Defect in Nanometer Technologies due to SADP Process. | Freddy Forero, Michel Renovell, Vctor H. Champac |
| 2017 | ETS | Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. | Amit Karel, Florence Azas, Mariane Comte, Jean-Marc Gallire, Michel Renovell, Keshav Singh |
| 2017 | ETS | Mitigating read & write errors in STT-MRAM memories under DVS. | Elena-Ioana Vatajelu, Rosa Rodrguez-Montas, Michel Renovell, Joan Figueras |
| 2016 | ETS | Behavior and test of open-gate defects in FinFET based cells. | Francisco Mesalles, Hector Villacorta, Michel Renovell, Vctor H. Champac |
| 2015 | DATE | Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell. | Elena I. Vatajelu, Rosa Rodrguez-Montas, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras |
| 2015 | ETS | Power-aware voltage tuning for STT-MRAM reliability. | Elena I. Vatajelu, Rosa Rodrguez-Montas, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras |
| 2014 | DATE | New implementions of predictive alternate analog/RF test with augmented model redundancy. | Haithem Ayari, Florence Azas, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell |
| 2014 | IOLTS | Solutions for the self-adaptation of communicating systems in operation. | Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azas, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos |
| 2013 | ETS | Implementing model redundancy in predictive alternate test to improve test confidence. | Haithem Ayari, Florence Azas, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell |
| 2012 | ITC | Making predictive analog/RF alternate test strategy independent of training set size. | Haithem Ayari, Florence Azas, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell |
| 2012 | VTS | Smart selection of indirect parameters for DC-based alternate RF IC testing. | Haithem Ayari, Florence Azas, Serge Bernard, Mariane Comte, Michel Renovell, Vincent Kerzerho, Olivier Potin, Christophe Kelma |
| 2011 | DDECS | Influence of parasitic memory effect on single-cell faults in SRAMs. | Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell |
| 2011 | VTS | A new methodology for realistic open defect detection probability evaluation under process variations. | Jess Moreno, Vctor H. Champac, Michel Renovell |
| 2009 | DDECS | An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. | Florence Azas, Yves Bertrand, Michel Renovell |
| 2009 | VTS | An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. | Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker |
| 2008 | ETS | A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. | Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker |
| 2008 | IOLTS | On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. | Florence Azas, Laurent Larguier, Yves Bertrand, Michel Renovell |
| 2007 | ETS | System-in-Package, a Combination of Challenges and Solutions. | Philippe Cauvet, Serge Bernard, Michel Renovell |
| 2007 | ETS | "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. | Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azas, Mariane Comte, Michel Renovell |
| 2006 | ETS | "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. | Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azas, Mariane Comte, Michel Renovell |
| 2006 | VTS | Functional Test of Field Programmable Analog Arrays. | Tiago R. Balen, Jos Vicente Calvano, Marcelo Lubaszewski, Michel Renovell |
| 2005 | VTS | Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. | Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azas, Michel Renovell |
| 2005 | VTS | Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. | Ilia Polian, Sandip Kundu, Jean-Marc Gallire, Piet Engelke, Michel Renovell, Bernd Becker |
| 2004 | ETS | Automatic test pattern generation for resistive bridging faults. | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker |
| 2004 | ETS | Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. | Patrick Girard, Olivier Hron, Serge Pravossoudovitch, Michel Renovell |
| 2004 | IOLTS | BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. | Patrick Girard, Olivier Hron, Serge Pravossoudovitch, Michel Renovell |
| 2004 | IOLTS | Scan Design and Secure Chip. | David Hly, Marie-Lise Flottes, Frdric Bancel, Bruno Rouzeyre, Nicolas Brard, Michel Renovell |
| 2004 | ITC | Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. | Tiago R. Balen, Antonio Andrade Jr., Florence Azas, Michel Renovell, Marcelo Lubaszewski |
| 2004 | VTS | An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. | Tiago R. Balen, Antonio Andrade Jr., Florence Azas, Marcelo Lubaszewski, Michel Renovell |
| 2004 | VTS | The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. | Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker |
| 2004 | VTS | A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. | Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure |
| 2003 | ETS | Requirements for delay testing of look-up tables in SRAM-based FPGAs. | Patrick Girard, Olivier Hron, Serge Pravossoudovitch, Michel Renovell |
| 2003 | ETS | Modeling feedback bridging faults with non-zero resistance. | Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker |
| 2003 | IOLTS | Defect Analysis for Delay-Fault BIST in FPGAs. | Patrick Girard, Olivier Hron, Serge Pravossoudovitch, Michel Renovell |
| 2003 | ITC | A New Methodology For ADC Test Flow Optimization. | Serge Bernard, Mariane Comte, Florence Azas, Yves Bertrand, Michel Renovell |
| 2003 | ITC | Simulating Resistive Bridging and Stuck-At Faults. | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker |
| 2002 | ETS | A high accuracy triangle-wave signal generator for on-chip ADC testing. | Serge Bernard, Florence Azas, Yves Bertrand, Michel Renovell |
| 2002 | ETS | Modeling gate oxide short defects in CMOS minimum transistors. | Michel Renovell, Jean Marc Gallire, Florence Azas, Yves Bertrand |
| 2001 | DATE | Implementation of a linear histogram BIST for ADCs. | Florence Azas, Serge Bernard, Yves Bertrand, Michel Renovell |
| 2001 | ITC | IS-FPGA : a new symmetric FPGA architecture with implicit scan. | Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 2001 | ITC | Boolean and current detection of MOS transistor with gate oxide short. | Michel Renovell, Jean Marc Gallire, Florence Azas, Serge Bernard, Yves Bertrand |
| 2001 | VTS | A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. | Florence Azas, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell |
| 2000 | DATE | Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. | rika F. Cota, Michel Renovell, Florence Azas, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski |
| 2000 | ETS | Towards an ADC BIST scheme using the histogram test technique. | Florence Azas, Serge Bernard, Y. Betrand, Michel Renovell |
| 2000 | ETS | Analyzing the test generation problem for an application-oriented test of FPGAs. | Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian |
| 2000 | FPL | A Specific Test Methodology for Symmetric SRAM-Based FPGAs. | Michel Renovell |
| 2000 | ITC | Different experiments in test generation for XILINX FPGAs. | Michel Renovell, Yervant Zorian |
| 2000 | VTS | Hardware Resource Minimization for Histogram-Based ADC BIST. | Michel Renovell, Florence Azas, Serge Bernard, Yves Bertrand |
| 1999 | DATE | Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1999 | ETS | Functional and structural testing of switched-current circuits. | Michel Renovell, Florence Azas, J.-C. Bodin, Yves Bertrand |
| 1999 | ETS | Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1999 | ITC | Optimal conditions for Boolean and current detection of floating gate faults. | Michel Renovell, Andr Ivanov, Yves Bertrand, Florence Azas, Sumbal Rafiq |
| 1998 | DATE | Novel Technique for Testing FPGAs. | Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi |
| 1998 | DATE | Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. | Michel Renovell, Florence Azas, Yves Bertrand |
| 1998 | DATE | RAM-Based FPGA's: A Test Approach for the Configurable Logic. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1998 | FPL | SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1998 | ITC | SRAM-based FPGA's: testing the LUT/RAM modules. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1998 | VTS | Design-For-Testability for Switched-Current Circuits. | Florence Azas, Michel Renovell, Yves Bertrand, J.-C. Bodin |
| 1997 | DATE | On-chip analog output response compaction. | Michel Renovell, Florence Azas, Yves Bertrand |
| 1997 | ITC | Test Strategy Sensitivity to Defect Parameters. | Michel Renovell, Yves Bertrand |
| 1997 | VTS | Test of RAM-based FPGA: methodology and application to the interconnect. | Michel Renovell, Joan Figueras, Yervant Zorian |
| 1996 | EDCC | The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault. | Michel Renovell, P. Huc, Yves Bertrand |
| 1996 | VTS | The multi-configuration: A DFT technique for analog circuits. | Michel Renovell, Florence Azas, Yves Bertrand |
| 1996 | VTS | Bridging fault coverage improvement by power supply control. | Michel Renovell, P. Huc, Yves Bertrand |
| 1995 | VTS | The concept of resistance interval: a new parametric model for realistic resistive bridging fault. | Michel Renovell, P. Huc, Yves Bertrand |
| 1994 | EDCC | The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds. | Michel Renovell, P. Huc, Yves Bertrand |
| 1994 | VTS | CMOS bridging fault modeling. | Michel Renovell, P. Huc, Yves Bertrand |
| 1993 | ITC | Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. | Yves Bertrand, Frdric Bancel, Michel Renovell |
| 1993 | VLSID | A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. | Yves Bertrand, Frdric Bancel, Michel Renovell |
| 1992 | VLSID | A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs. | Michel Renovell, M. Ildevert, Yves Bertrand |