Serge Pravossoudovitch
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
69
Venues
10
Active years
1992–2014
Best venue rank
A*
Where they publish
Papers
69 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2014 | DDECS | Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. | Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel |
| 2013 | IOLTS | SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. | Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frdric Saign |
| 2012 | VTS | Advanced test methods for SRAMs. | Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel |
| 2011 | DDECS | On using a SPICE-like TSTAC™ eFlash model for design and test. | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benot Godard, Gilles Festes, Laurent Vachez |
| 2011 | DDECS | A study of path delay variations in the presence of uncorrelated power and ground supply noise. | Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel |
| 2011 | DDECS | Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. | Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2011 | ETS | A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. | Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Snchez, Mauricio de Carvalho, Matteo Sonza Reorda |
| 2011 | ITC | On using address scrambling to implement defect tolerance in SRAMs. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2010 | DAC | A statistical simulation method for reliability analysis of SRAM core-cells. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2010 | DDECS | Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. | Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen |
| 2010 | ETS | Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2010 | ETS | Setting test conditions for improving SRAM reliability. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2010 | ETS | A two-layer SPICE model of the ATMEL TSTAC | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benot Godard, Gilles Festes, Laurent Vachez |
| 2010 | ITC | Parity prediction synthesis for nano-electronic gate designs. | D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich |
| 2010 | ITC | Is test power reduction through X-filling good enough? | Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed |
| 2010 | VTS | Detecting NBTI induced failures in SRAM core-cells. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2009 | DATE | A new design-for-test technique for SRAM core-cell stability faults. | Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin |
| 2009 | DDECS | Comprehensive bridging fault diagnosis based on the SLAT paradigm. | Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute |
| 2009 | DDECS | An efficient fault simulation technique for transition faults in non-scan sequential circuits. | Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda |
| 2009 | ITC | NAND flash testing: A preliminary study on actual defects. | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benot Godard |
| 2008 | DATE | A Design-for-Diagnosis Technique for SRAM Write Drivers. | Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin |
| 2008 | DDECS | SoC Symbolic Simulation: a case study on delay fault testing. | Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi |
| 2008 | IOLTS | Yield Improvement, Fault-Tolerance to the Rescue?. | Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2008 | ITC | A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. | Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
| 2008 | ITC | SoC Yield Improvement: Redundant Architectures to the Rescue? | Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2008 | VTS | An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. | Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin |
| 2007 | DATE | Slow write driver faults in 65nm SRAM technology: analysis and March test solution. | Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
| 2007 | DDECS | A Mixed Approach for Unified Logic Diagnosis. | Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2007 | ETS | Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. | Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2007 | ETS | Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. | Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
| 2007 | ETS | DERRIC: A Tool for Unified Logic Diagnosis. | Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2007 | ITC | A concurrent approach for testing address decoder faults in eFlash memories. | Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga |
| 2007 | VTS | Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. | Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2007 | VTS | Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. | Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
| 2006 | DDECS | March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
| 2006 | VTS | An Overview of Failure Mechanisms in Embedded Flash Memories. | Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2005 | DAC | Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 m and 90 nm technologies. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
| 2005 | ETS | Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan |
| 2005 | VTS | Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan |
| 2004 | DATE | Design of Routing-Constrained Low Power Scan Chains. | Yannick Bonhomme, Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2004 | ETS | Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan |
| 2004 | ETS | Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. | Patrick Girard, Olivier Hron, Serge Pravossoudovitch, Michel Renovell |
| 2004 | IOLTS | BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. | Patrick Girard, Olivier Hron, Serge Pravossoudovitch, Michel Renovell |
| 2004 | VTS | March iC-: An Improved Version of March C- for ADOFs Detection. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri |
| 2003 | ETS | Defect-oriented dynamic fault models for embedded-SRAMs. | Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel |
| 2003 | ETS | Requirements for delay testing of look-up tables in SRAM-based FPGAs. | Patrick Girard, Olivier Hron, Serge Pravossoudovitch, Michel Renovell |
| 2003 | IOLTS | Defect Analysis for Delay-Fault BIST in FPGAs. | Patrick Girard, Olivier Hron, Serge Pravossoudovitch, Michel Renovell |
| 2003 | ITC | Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. | Yannick Bonhomme, Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch |
| 2002 | ITC | Power Driven Chaining of Flip-Flops in Scan Architectures. | Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch |
| 2002 | VTS | On Using Efficient Test Sequences for BIST. | Ren David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2001 | ETS | On hardware generation of random single input change test sequences. | Ren David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2001 | IOLTS | A Gated Clock Scheme for Low Power Scan-Based BIST. | Yannick Bonhomme, Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch |
| 2001 | VTS | A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. | Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich |
| 2000 | ETS | Delay fault testing: choosing between random SIC and random MIC test sequences. | Arnaud Virazel, Ren David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch |
| 2000 | IOLTS | Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2000 | ITC | Low power BIST design by hypergraph partitioning: methodology and architectures. | Patrick Girard, Christian Landrault, Los Guiller, Serge Pravossoudovitch |
| 1999 | ETS | Low power BIST by filtering non-detecting vectors. | Salvador Manich, A. Gabarr, M. Lopez, Joan Figueras, Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch, Joo Paulo Teixeira, Marcelino B. Santos |
| 1999 | ISCAS | Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. | Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, Joo Paulo Teixeira, Marcelino B. Santos |
| 1999 | VTS | A Test Vector Inhibiting Technique for Low Energy BIST Design. | Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch |
| 1997 | ISLPED | A gate resizing technique for high reduction in power consumption. | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac |
| 1997 | VTS | An optimized BIST test pattern generator for delay testing. | Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch |
| 1996 | DATE | DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. | P. Cavallera, Patrick Girard, Christian Landrault, Serge Pravossoudovitch |
| 1996 | ITC | A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez |
| 1996 | VTS | A new test pattern generation method for delay fault testing. | S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch |
| 1995 | DATE | A trace-based method for delay fault diagnosis in synchronous sequential circuits. | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez |
| 1995 | VTS | Diagnostic of path and gate delay faults in non-scan sequential circuits. | Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez |
| 1993 | ITC | An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. | D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch |
| 1992 | DAC | A Novel Approach to Delay-Fault Diagnosis. | Patrick Girard, Christian Landrault, Serge Pravossoudovitch |
| 1992 | VLSID | A New Reliable Method for Delay-Fault Diagnosis. | Marie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch |