| 2026 | DATE | COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events. | Mahmudul Hasan, Sudipta Paria, Swarup Bhunia, Tamzidul Hoque |
| 2026 | FPGA | PROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros. | Pravin Gaikwad, Aritra Dasgupta, Sudipta Paria, Peyman Dehghanzadeh, Jonathan Cruz, Swarup Bhunia |
| 2026 | VTS | VTS2026 Contest Publication: TTTC's E.J. McCluskey Best Doctoral Thesis Award. | Luca Benini, Paolo Bernardi, Alberto Bosio, Swarup Bhunia, Riccardo Cantoro, Degang Chen, Krishnendu Chakrabarty, Jayeeta Chaudhuri, Bastien Deveautour, Gabriele Filipponi, Angelo Garofalo, Salvatore Pappalardo, Sudipta Paria, Michael Rogenmoser, Philippe Sauter, Michael Sekyere, Chen Wu |
| 2026 | VTS | Exploring Agentic LLM Paradigms for Hardware Verification across Abstraction Levels. | Sudipta Paria, Swarup Bhunia |
| 2025 | DAC | POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel Leakage. | Tanzim Mahfuz, Sudipta Paria, Tasneem Suha, Swarup Bhunia, Prabuddha Chakraborty |
| 2025 | ICCAD | PROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed Generation. | Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Swarup Bhunia, Sai Manoj P. D. |
| 2025 | ICCD | FV-PAL: Scalable Formal Verification through Partitioning and LLM-Guided Property Generation. | Sudipta Paria, Aritra Dasgupta, Dinesh Reddy Ankireddy, Prabuddha Chakraborty, Swarup Bhunia |
| 2025 | ITC | LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency. | Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia |
| 2025 | VTS | CLIP: A Structural Approach to Cut Points Matching for Logic Equivalence Checking. | Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia |
| 2025 | VTS | SALTY: Explainable Artificial Intelligence Guided Structural Analysis for Hardware Trojan Detection. | Tanzim Mahfuz, Pravin Gaikwad, Tasneem Suha, Swarup Bhunia, Prabuddha Chakraborty |
| 2025 | VTS | Towards Automated Verification of IP and COTS: Leveraging LLMs in Pre- and Post-Silicon Stages. | Sudipta Paria, Aritra Dasgupta, Swarup Bhunia |
| 2023 | IJCNN | Energy Efficient Memory-based Inference of LSTM by Exploiting FPGA Overlay. | Krishnendu Guha, Amit Ranjan Trivedi, Swarup Bhunia |
| 2023 | VLSID | Unifying Intrinsically-Operated Physically Unclonable Function and Random Number Generation in Analog Circuits: A Case Study on Successive Approximation ADC. | Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi |
| 2023 | VTS | An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware. | Jackson Fugate, Greg Stitt, Naren Vikram Raj Masna, Aritra Dasgupta, Swarup Bhunia, Nij Dorairaj, David Kehlet |
| 2022 | ASPDAC | FORTIFY: Analytical Pre-Silicon Side-Channel Characterization of Digital Designs. | A. V. Lakshmy, Chester Rebeiro, Swarup Bhunia |
| 2022 | DAC | VIPR-PCB: a machine learning based golden-free PCB assurance framework. | Aritra Bhattacharyay, Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia |
| 2022 | ICCAD | Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool. | Swarup Bhunia, Amitabh Das, Saverio Fazzari, Vivian Kammler, David Kehlet, Jeyavijayan Rajendran, Ankur Srivastava |
| 2022 | ITC | AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks. | Prabuddha Chakraborty, Swarup Bhunia |
| 2022 | VLSID | SEVA: Structural Analysis based Security Evaluation of Sequential Locking. | Abdulrahman Alaql, Aritra Dasgupta, Md. Moshiur Rahman, Swarup Bhunia |
| 2021 | DATE | CASTLE: Architecting Assured System-on-Chip Firmware Integrity. | Sandip Ray, Atul Prasad Deb Nath, Kshitij Raj, Swarup Bhunia |
| 2020 | DATE | SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in Hardware. | Milind Srivastava, Patanjali SLPSK, Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia |
| 2020 | VTC | P2C2: Peer-to-Peer Car Charging. | Prabuddha Chakraborty, Robert Parker, Tamzidul Hoque, Jonathan Cruz, Swarup Bhunia |
| 2019 | DAC | The Metric Matters: The Art of Measuring Trust in Electronics. | Jonathan Cruz, Prabhat Mishra, Swarup Bhunia |
| 2019 | ICCAD | SCR-QRNG: Side-Channel Resistant Design using Quantum Random Number Generator. | Jungmin Park, Seongjoon Cho, Taejin Lim, Swarup Bhunia, Mark Tehranipoor |
| 2019 | ITC | IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future. | Domenic Forte, Swarup Bhunia, Ramesh Karri, Jim Plusquellic, Mark Tehranipoor |
| 2019 | VTS | Quality Obfuscation for Error-Tolerant and Adaptive Hardware IP Protection. | Abdulrahman Alaql, Tamzidul Hoque, Domenic Forte, Swarup Bhunia |
| 2019 | VTS | Special Session: Countering IP Security threats in Supply chain. | Hassan Salmani, Tamzidul Hoque, Swarup Bhunia, Muhammad Yasin, Jeyavijayan (JV) Rajendran, Naghmeh Karimi |
| 2018 | ASPDAC | System-on-chip security architecture and CAD framework for hardware patch. | Atul Prasad Deb Nath, Sandip Ray, Abhishek Basak, Swarup Bhunia |
| 2018 | DATE | An automated configurable Trojan insertion framework for dynamic trust benchmarks. | Jonathan Cruz, Yuanwen Huang, Prabhat Mishra, Swarup Bhunia |
| 2018 | ISLPED | Intrinsic and Database-free Watermarking in ICs by Exploiting Process and Design Dependent Variability in Metal-Oxide-Metal Capacitances. | Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi |
| 2018 | ITC | Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify. | Tamzidul Hoque, Jonathan Cruz, Prabuddha Chakraborty, Swarup Bhunia |
| 2018 | VTS | Hardware Trojan attacks in embedded memory. | Tamzidul Hoque, Xinmu Wang, Abhishek Basak, Robert Karam, Swarup Bhunia |
| 2017 | ASPDAC | Security vulnerability analysis of design-for-test exploits for asset protection in SoCs. | Gustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, Mark Tehranipoor |
| 2017 | ASPDAC | MUTARCH: Architectural diversity for FPGA device and IP security. | Robert Karam, Tamzidul Hoque, Sandip Ray, Mark Tehranipoor, Swarup Bhunia |
| 2016 | ASPDAC | JTAG-based robust PCB authentication for protection against counterfeiting attacks. | Andrew Hennessy, Yu Zheng, Swarup Bhunia |
| 2016 | CCS | MERS: Statistical Test Generation for Side-Channel Analysis based Trojan Detection. | Yuanwen Huang, Swarup Bhunia, Prabhat Mishra |
| 2016 | DAC | Exploiting design-for-debug for flexible SoC security architecture. | Abhishek Basak, Swarup Bhunia, Sandip Ray |
| 2016 | DATE | Current based PUF exploiting random variations in SRAM cells. | Fengchao Zhang, Shuo Yang, Jim Plusquellic, Swarup Bhunia |
| 2016 | FPGA | ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric (Abstact Only). | Wenchao Qian, Christopher Babecki, Robert Karam, Swarup Bhunia |
| 2016 | ICCAD | On detecting delay anomalies introduced by hardware trojans. | Dylan Ismari, Jim Plusquellic, Charles Lamech, Swarup Bhunia, Fareena Saqib |
| 2016 | ICCD | The power play: Security-energy trade-offs in the IoT regime. | Sandip Ray, Tamzidul Hoque, Abhishek Basak, Swarup Bhunia |
| 2016 | VTS | Security validation in IoT space. | Sandip Ray, Swarup Bhunia, Yier Jin, Mark Tehranipoor |
| 2015 | DAC | Self-correcting STTRAM under magnetic field attacks. | Jae-Won Jang, Jongsun Park, Swaroop Ghosh, Swarup Bhunia |
| 2015 | DAC | Correctness and security at odds: post-silicon validation of modern SoC designs. | Sandip Ray, Jin Yang, Abhishek Basak, Swarup Bhunia |
| 2015 | ICCAD | A Flexible Architecture for Systematic Implementation of SoC Security Policies. | Abhishek Basak, Swarup Bhunia, Sandip Ray |
| 2015 | ITC | PiRA: IC authentication utilizing intrinsic variations in pin resistance. | Abhishek Basak, Fengchao Zhang, Swarup Bhunia |
| 2015 | VLSID | Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems. | Prabhat Mishra, Swarup Bhunia, Srivaths Ravi |
| 2015 | VTS | Robust counterfeit PCB detection exploiting intrinsic trace impedance variations. | Fengchao Zhang, Andrew Hennessy, Swarup Bhunia |
| 2014 | DAC | CACI: Dynamic Current Analysis Towards Robust Recycled Chip Identification. | Yu Zheng, Abhishek Basak, Swarup Bhunia |
| 2014 | DATE | Toward ultralow-power computing at exteme with silicon carbide (SiC) nanoelectromechanical logic. | Swarup Bhunia, Vaishnavi Nattar Ranganathan, Tina He, Srihari Rajgopal, Rui Yang, Mehran Mehregany, Philip X.-L. Feng |
| 2014 | DATE | Energy-efficient hardware acceleration through computing in the memory. | Somnath Paul, Robert Karam, Swarup Bhunia, Ruchir Puri |
| 2014 | ICCAD | A non-volatile memory based physically unclonable function without helper data. | Wenjie Che, Jim Plusquellic, Swarup Bhunia |
| 2014 | VTS | Active defense against counterfeiting attacks through robust antifuse-based on-chip locks. | Abhishek Basak, Yu Zheng, Swarup Bhunia |
| 2013 | ASPDAC | ScanPUF: Robust ultralow-overhead PUF using scan chain. | Yu Zheng, Aswin Raghav Krishna, Swarup Bhunia |
| 2013 | DAC | Role of power grid in side channel attack and power-grid-aware secure design. | Xinmu Wang, Wen Yueh, Debapriya Basu Roy, Seetharam Narasimhan, Yu Zheng, Saibal Mukhopadhyay, Debdeep Mukhopadhyay, Swarup Bhunia |
| 2013 | DAC | RESP: a robust physical unclonable function retrofitted into embedded SRAM array. | Yu Zheng, Maryamsadat Hashemian, Swarup Bhunia |
| 2013 | VLSID | Dynamic Cache Tuning for Efficient Memory Based Computing in Multicore Architectures. | Hadi Hajimiri, Prabhat Mishra, Swarup Bhunia |
| 2013 | VLSID | Ultralow-Power and Robust Embedded Memory for Bioimplantable Microsystems. | Maryamsadat Hashemian, Swarup Bhunia |
| 2012 | VLSID | Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks. | Anandaroop Ghosh, Somnath Paul, Swarup Bhunia |
| 2012 | VLSID | Tutorial T4: Intellectual Property Protection and Security in System-on-Chip Design. | Susmita Sur-Kolay, Swarup Bhunia |
| 2012 | VLSID | SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation. | Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Swarup Bhunia |
| 2012 | VLSID | Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory. | Lei Wang, Somnath Paul, Swarup Bhunia |
| 2011 | CHES | MECCA: A Robust Low-Overhead PUF Using Embedded Memory Array. | Aswin Raghav Krishna, Seetharam Narasimhan, Xinmu Wang, Swarup Bhunia |
| 2011 | DATE | Multi-level attacks: An emerging security concern for cryptographic hardware. | Subidh Ali, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Swarup Bhunia |
| 2011 | DATE | High-temperature (>500°C) reconfigurable computing using silicon carbide NEMS switches. | Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Francis G. Wolff, Srihari Rajgopal, Te-Hao Lee, Mehran Mehregany, Swarup Bhunia |
| 2011 | FPGA | Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only). | Somnath Paul, Swarup Bhunia |
| 2011 | ICCD | Sequential hardware Trojan: Side-channel aware design and placement. | Xinmu Wang, Seetharam Narasimhan, Aswin Raghav Krishna, Tatini Mal-Sarkar, Swarup Bhunia |
| 2011 | VLSID | VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width. | Keerthi Kunaparaju, Seetharam Narasimhan, Swarup Bhunia |
| 2010 | CHES | Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection. | Dongdong Du, Seetharam Narasimhan, Rajat Subhra Chakraborty, Swarup Bhunia |
| 2010 | IOLTS | Trustworthy computing in a multi-core system using distributed scheduling. | David R. McIntyre, Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia |
| 2010 | ISLPED | VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement. | Somnath Paul, Swarup Bhunia |
| 2010 | VLSID | RTL Hardware IP Protection Using Key-Based Control and Data Flow Obfuscation. | Rajat Subhra Chakraborty, Swarup Bhunia |
| 2010 | VTS | Special session 11B: Hot topic hardware security: Design, test and verification issues. | Swarup Bhunia, Anand Raghunathan |
| 2009 | CHES | MERO: A Statistical Approach for Hardware Trojan Detection. | Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia |
| 2009 | ICCAD | Security against hardware Trojan through a novel application of design obfuscation. | Rajat Subhra Chakraborty, Swarup Bhunia |
| 2009 | ICCAD | A circuit-software co-design approach for improving EDP in reconfigurable frameworks. | Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia |
| 2009 | ICCAD | A variation-aware preferential design approach for memory based reconfigurable computing. | Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia |
| 2008 | ASPDAC | MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. | Somnath Paul, Swarup Bhunia |
| 2008 | DAC | Collective computing based on swarm intelligence. | Seetharam Narasimhan, Somnath Paul, Swarup Bhunia |
| 2008 | DAC | Reconfigurable computing using content addressable memory for improved performance and resource usage. | Somnath Paul, Swarup Bhunia |
| 2008 | DATE | Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction. | Lawrence Leinweber, Swarup Bhunia |
| 2008 | DATE | Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme. | Francis G. Wolff, Christos A. Papachristou, Swarup Bhunia, Rajat Subhra Chakraborty |
| 2008 | DATE | Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. | Yu Zhou, Somnath Paul, Swarup Bhunia |
| 2008 | ICCAD | Hardware protection and authentication through netlist level obfuscation. | Rajat Subhra Chakraborty, Swarup Bhunia |
| 2008 | ICCAD | Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. | Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia |
| 2008 | ISLPED | Low power design under parameter variations. | Swarup Bhunia, Kaushik Roy |
| 2008 | VLSID | Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. | Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia |
| 2007 | ASPDAC | Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube Switches. | Swarup Bhunia, Massood Tabib-Azar, Daniel G. Saab |
| 2007 | DATE | Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy |
| 2007 | ICCAD | Low-overhead design technique for calibration of maximum frequency at multiple operating points. | Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia |
| 2007 | ICCD | Memory based computation using embedded cache for processor yield and reliability improvement. | Somnath Paul, Swarup Bhunia |
| 2007 | IOLTS | Tolerance to Small Delay Defects by Adaptive Clock Stretching. | Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy |
| 2007 | IOLTS | Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. | Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia |
| 2007 | ISLPED | Low power FPGA design using hybrid CMOS-NEMS approach. | Yu Zhou, Shijo Thekkel, Swarup Bhunia |
| 2007 | ITC | Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions. | Swarup Bhunia, Kaushik Roy |
| 2007 | VLSID | Process Variations and Process-Tolerant Design. | Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy |
| 2007 | VTS | VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. | Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia |
| 2006 | ASPDAC | Speed binning aware design methodology to improve profit under parameter variations. | Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy |
| 2006 | ASPDAC | Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. | Ashish Goel, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy |
| 2006 | DATE | Low power synthesis of dynamic logic circuits using fine-grained clock gating. | Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia |
| 2006 | DATE | Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. | Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy |
| 2006 | ICCAD | A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. | Swaroop Ghosh, Swarup Bhunia, Kaushik Roy |
| 2006 | IOLTS | Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. | Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy |
| 2005 | DAC | A novel synthesis approach for active leakage power reduction using dynamic supply gating. | Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy |
| 2005 | DATE | A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. | Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy |
| 2005 | DATE | Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy |
| 2005 | DATE | Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. | Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy |
| 2005 | ETS | A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points. | Arijit Raychowdhury, Swaroop Ghosh, Swarup Bhunia, Debjyoti Ghosh, Kaushik Roy |
| 2005 | ICCD | Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. | Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy |
| 2005 | IOLTS | Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. | Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy |
| 2005 | ISLPED | Effectiveness of low power dual-V | Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy |
| 2005 | VTS | Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. | Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy |
| 2004 | DATE | Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis. | Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy |
| 2004 | ICCD | A Novel Low-Power Scan Design Technique Using Supply Gating. | Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy |
| 2004 | IOLTS | A Technique to Reduce Power and Test Application Time in BIST. | Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy |
| 2003 | DATE | Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. | Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy |
| 2003 | HPCA | Deterministic Clock Gating for Microprocessor Power Reduction. | Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy |
| 2002 | DAC | A novel wavelet transform based transient current analysis for fault detection and localization. | Swarup Bhunia, Kaushik Roy, Jaume Segura |
| 2002 | DATE | Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis. | Swarup Bhunia, Kaushik Roy |
| 2002 | ICIP | Content based image retrieval: related issues using Euler vector. | Arijit Bishnu, Swarup Bhunia, C. A. Murthy, Bhargab B. Bhattacharya, Malay Kumar Kundu, Tinku Acharya |
| 2002 | VTS | Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform. | Swarup Bhunia, Kaushik Roy |
| 2000 | VLSID | Topological Routing Amidst Polygonal Obstacles. | Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya |
| 1999 | VLSID | Design, Simulation and Synthesis of an ASIC for Fractal Image Compression. | Swarup Bhunia, Soumya K. Ghosh, Pramod Kumar, Partha Pratim Das, Jayanta Mukherjee |