| 2026 | ACL | Revisiting Evaluation of Question Answering Systems in Low-Resource Indic Languages: Bridging Human and Metric Alignment. | Anuj Kumar, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh |
| 2026 | DDECS | A SAT-Hard Compound Logic Locking Scheme with Empirical Resistance to Known Structural Attacks. | Sonali Shukla, Govind Rajhans Jadhav, Durgesh Sardan, Suryakant Toraskar, Jaynarayan T. Tudu, Makoto Ikeda, Masahiro Fujita, Virendra Singh |
| 2026 | ICAART | DREAM: Dynamic, Reinforced, and Evasive Attack Model on Spatio-Temporal GNNs. | Mandru Suma Sri, Uddhav Narayan Gilda, Tarun Bisht, Virendra Singh |
| 2026 | ICAART | Sparse Rewards as Preferences: Investigating Reward Shaping with Preference-Based RL Methods in Sparse Reward Domains. | Veerendrababu Vakkapatla, Shariq Faraz, Virendra Singh |
| 2026 | ICS | Continuation-Preserving Tiling for Pointer-Chasing Optimization in Structured Mutual Recursion. | Avinash Kumar, Virendra Singh, Supratim Biswas |
| 2026 | SECRYPT | SPARTON: Secure Dynamic Partition Scheme for Last-Level Cache. | Tejeshwar Bhagatsing Thorawade, Rishab Ravi, Varun Venkitaraman, Keerthisagar Kokkiligadda, Nirmal Kumar Boran, Virendra Singh |
| 2025 | IJCNLP | Video-guided Machine Translation: A Survey of Models, Datasets, and Challenges. | Pinaki Das, Virendra Singh, Pushpak Bhattacharyya, Gholamreza Haffari |
| 2025 | IOLTS | GPD: Predictive Control Flow Error Detection Leveraging Data Flow Error Detection Methods. | Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh |
| 2025 | ISCAS | A New Hardware Trojan Attack on Scan-obfuscated Logic-locked Circuits. | Anjum Riaz, Gaurav Kumar, Yamuna Prasad, Satyadev Ahlawat, Virendra Singh |
| 2025 | ISCAS | RRR: Robust runtime reconfigurable shared cache management scheme for GPGPUs. | Varun Venkitaraman, Shrasti Bhargava, Tejeshwar Bhagatsing Thorawade, Keerthisagar Kokkiligadda, Rahul Kumar, Virendra Singh |
| 2025 | ITC | Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time. | Jaidev Shenoy, Virendra Singh, Kelly Ockunzzi |
| 2025 | VLSID | Lichen: Leveraging Coupled Heterogeneity. | Prakhar Diwan, Nirmal Kumar Boran, Virendra Singh |
| 2025 | SBAC-PAD | TRAP: Time-Aware Probabilistic In-Dram RowHammer Solution. | Samiksha Verma, Virendra Singh |
| 2025 | SECRYPT | Stegoslayer: A Robust Browser-Integrated Approach for Thwarting Stegomalware. | Rushikesh Kawale, Sarath Babu, Virendra Singh |
| 2025 | SECRYPT | EDQKD: Enhanced-Dynamic Quantum Key Distributions with Improved Security and Key Rate. | Nikhil Kumar Parida, Sarath Babu, Neeraj Panwar, Virendra Singh |
| 2025 | SECRYPT | SCAM: Secure Shared Cache Partitioning Scheme to Enhance Throughput of CMPs. | Varun Venkitaraman, Rishab Ravi, Tejeshwar Bhagatsing Thorawade, Nirmal Kumar Boran, Virendra Singh |
| 2024 | DDECS | TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection. | Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh |
| 2024 | HPCC | HIDC: Heterogeneous-ISA Dynamic Core. | Nirmal Kumar Boran, Prakhar Diwan, Meet Udeshi, Shubhankit Rathore, Virendra Singh |
| 2024 | ICAART | GNNDLD: Graph Neural Network with Directional Label Distribution. | Chandramani Chaudhary, Nirmal Kumar Boran, N. Sangeeth, Virendra Singh |
| 2024 | ICISS | MALAI: ML-Based Attack on Learning with Error Problem. | Mandru Suma Sri, Chakka Srikanth Yadav, Tikaram Sanyashi, Virendra Singh |
| 2024 | VLSID | Early Execution for Soft Error Detection. | Raj Kumar Choudhary, Janeel Patel, Virendra Singh |
| 2024 | VLSID | MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures. | Prakhar Diwan, Suryakant Toraskar, Varun Venkitaraman, Nirmal Kumar Boran, Chandramani Chaudhary, Virendra Singh |
| 2024 | SBAC-PAD | S-Clflush: Securing Against Flush-based Cache Timing Side-Channel Attacks. | Tejeshwar Bhagatsing Thorawade, Prajakta Yeola, Varun Venkitaraman, Virendra Singh |
| 2024 | SIN | Critical Behavior Sequence Monitoring for Early Malware Detection. | Tarun Bisht, Sarath Babu, Virendra Singh |
| 2023 | ICISS | Secure KNN Computation on Cloud. | Tikaram Sanyashi, Nirmal Kumar Boran, Virendra Singh |
| 2023 | IOLTS | ERrOR: Improving Performance and Fault Tolerance Using Early Execution. | Raj Kumar Choudhary, Janeel Patel, Virendra Singh |
| 2023 | IOLTS | On-Chip SRAM Disclosure Attack Prevention Technique for SoC. | Prokash Ghosh, Yogesh Gholap, Virendra Singh |
| 2023 | IOLTS | TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture. | Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh |
| 2022 | VTS | Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries. | Riccardo Cantoro, Francesco Garau, Riccardo Masante, Sandro Sartoni, Virendra Singh, Matteo Sonza Reorda |
| 2022 | SECRYPT | PASS-P: Performance and Security Sensitive Dynamic Cache Partitioning. | Nirmal Kumar Boran, Pranil Joshi, Virendra Singh |
| 2021 | ISCAS | Dynamic Optimizations in GPU Using Roofline Model. | Winnie Thomas, Suryakant Toraskar, Virendra Singh |
| 2020 | ISPASS | Characterization of Data Generating Neural Network Applications on x86 CPU Architecture. | Antara Ganguly, Shankar Balachandran, Anant V. Nori, Virendra Singh, Sreenivas Subramoney |
| 2020 | VLSID | A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. | Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh |
| 2019 | ICCD | Freeflow Core: Enhancing Performance of In-Order Cores with Energy Efficiency. | Raj Kumar Choudhary, Newton Singh, Harideep Nair, Rishabh Rawat, Virendra Singh |
| 2019 | IOLTS | Securing Scan through Plain-text Restriction. | Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh |
| 2019 | VLSID | A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. | Binod Kumar, Masahiro Fujita, Virendra Singh |
| 2019 | VLSID | On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time. | Jaidev Shenoy, Kelly Ockunzzi, Virendra Singh, Kushal Kamal |
| 2018 | DATE | ATPG power guards: On limiting the test power below threshold. | Rohini Gulve, Virendra Singh |
| 2018 | ISCAS | A PAM-4 10S/12S line coding scheme with equi-probable levels. | Sandeep Goyal, Ron Joseph, Virendra Singh, Shalabh Gupta |
| 2018 | ISCAS | In-situ Monitoring for Slack Time Violation Without Performance Penalty. | Nihar Hage, Satyadev Ahlawat, Virendra Singh |
| 2018 | ISCAS | On Securing Scan Design Through Test Vector Encryption. | Darshit Vaghani, Satyadev Ahlawat, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh |
| 2017 | ETS | An efficient test technique to prevent scan-based side-channel attacks. | Satyadev Ahlawat, Darshit Vaghani, Virendra Singh |
| 2017 | ICCD | DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching. | Newton, Sujit Kr Mahto, Suhit Pai, Virendra Singh |
| 2017 | IOLTS | Revisiting random access scan for effective enhancement of post-silicon observability. | Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh |
| 2017 | IOLTS | Instruction-based self-test for delay faults maximizing operating temperature. | Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh |
| 2017 | IOLTS | Test pattern generation to detect multiple faults in ROBDD based combinational circuits. | Toral Shah, Anzhela Yu. Matrosova, Virendra Singh |
| 2017 | ISCAS | A low cost technique for scan chain diagnosis. | Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh |
| 2017 | ITC | Exploiting path delay test generation to develop better TDF tests for small delay defects. | Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja |
| 2017 | VLSID | On Testing of Superscalar Processors in Functional Mode for Delay Faults. | Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh |
| 2017 | VLSID | A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. | Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita |
| 2016 | IOLTS | A high performance scan flip-flop design for serial and mixed mode scan test. | Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh |
| 2016 | IOLTS | REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture. | Shoba Gopalakrishnan, Virendra Singh |
| 2015 | ICCD | Application behavior aware re-reference interval prediction for shared LLC. | Parth Lathigara, Shankar Balachandran, Virendra Singh |
| 2014 | VLSID | Operand Isolation with Reduced Overhead for Low Power Datapath Design. | Lokesh Siddhu, Amit Mishra, Virendra Singh |
| 2013 | VLSID | Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. | Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal |
| 2012 | IOLTS | SEU tolerant robust memory cell design. | Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita |
| 2012 | ISCAS | Impact of process variations on computers used for image processing. | Suraj Sindia, Fa Foster Dai, Vishwani D. Agrawal, Virendra Singh |
| 2012 | VTS | Derating based hardware optimizations in soft error tolerant designs. | V. Prasanth, Virendra Singh, Rubin A. Parekhji |
| 2012 | SIN | Efficient regular expression pattern matching for network intrusion detection systems using modified word-based automata. | Pawan Kumar, Virendra Singh |
| 2011 | DSN | Level of confidence evaluation and its usage for Roll-back Recovery with Checkpointing optimization. | Dimitar Nikolov, Urban Ingelsson, Virendra Singh, Erik Larsson |
| 2011 | HPCC | Parallelizing TUNAMI-N1 Using GPGPU. | Harsh Gidra, Israrul Haque, Nitin P. Kumar, M. Sargurunathan, Manoj Singh Gaur, Vijay Laxmi, Mark Zwolinski, Virendra Singh |
| 2011 | ICCD | Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
| 2011 | IOLTS | Reduced overhead soft error mitigation using error control coding techniques. | V. Prasanth, Virendra Singh, Rubin A. Parekhji |
| 2011 | VTS | Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. | Suraj Sindia, Vishwani D. Agrawal, Virendra Singh |
| 2010 | DATE | Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
| 2010 | DSN | Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
| 2010 | ETS | Modified T-Flip-Flop based scan cell for RAS. | Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh |
| 2010 | ETS | Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara |
| 2010 | IOLTS | Robust detection of soft errors using delayed capture methodology. | V. Prasanth, Virendra Singh, Rubin A. Parekhji |
| 2010 | ISCAS | Test application time minimization for RAS using basis optimization of column decoder. | A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh |
| 2010 | ISCAS | Genetic algorithm based topology generation for application specific Network-on-Chip. | Naveen Choudhary, Manoj Singh Gaur, Vijay Laxmi, Virendra Singh |
| 2010 | VLSID | On Minimization of Test Application Time for RAS. | Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh |
| 2010 | VLSID | Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. | Suraj Sindia, Virendra Singh, Vishwani D. Agrawal |
| 2009 | DATE | Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. | Mikael Vyrynen, Virendra Singh, Erik Larsson |
| 2009 | ETS | On Minimization of Peak Power for Scan Circuit during Test. | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal |
| 2005 | FPL | Testing Superscalar Processors in Functional Mode. | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
| 2005 | ISCAS | Instruction-based delay fault self-testing of pipelined processor cores. | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
| 2004 | VLSID | Instruction-Based Delay Fault Self-Testing of Processor Cores. | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |