Skip to content

Xiaoqing Wen

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

73

Venues

15

Active years

1990–2026

Best venue rank

A*

Where they publish

Papers

73 indexed papers, newest first.

YearVenueTitleAuthors
2026ISCASAlgorithm-Aided Design and Verification for Multiple-Node-Upset-Recovery Latches.Zhiyuan Pei, Jing Li, Haroon Waris, M. Shahzad Younis, Aibin Yan, Jiahui Deng, Yilin Gui, Xiaoqing Wen
2025DATEEfficient Modulated State Space Model for Mixed-Type Wafer Defect Pattern Recognition.Mu Nie, Shidong Zhu, Aibin Yan, Cheng Zhuo, Xiaoqing Wen, Tianming Ni
2025DATENVSRLO: A FeFET-Based Non-Volatile and SEU-Recoverable Latch Design with Optimized Overhead.Aibin Yan, Wangjin Jiang, Han Bao, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard
2025EuroSysAchilles: Efficient TEE-Assisted BFT Consensus via Rollback Resilient Recovery.Jianyu Niu, Xiaoqing Wen, Guanlong Wu, Shengqi Liu, Jiangshan Yu, Yinqian Zhang
2025ISCASTNURML: Triple-Node-Upset-Recovery Magnetic Latch Design with Non-Volatility for Aerospace Applications.Aibin Yan, Zhiyuan Pei, Xing Guo, Jie Song, Cuiyun Jiang, Huaguo Liang, Xiaoqing Wen, Patrick Girard
2024ISCASNonvolatile and SEU-Recoverable Latch Based on FeFET and CMOS for Energy-Harvesting Devices.Aibin Yan, Zhuoyuan Lin, Guangzhu Liu, Qingyang Zhang, Zhengfeng Huang, Jie Cui, Xiaoqing Wen, Patrick Girard
2023DATEHigh Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology.Aibin Yan, Zhen Zhou, Liang Ding, Jie Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard
2023ETSBiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell.Stefan Holst, Ruijun Ma, Xiaoqing Wen, Aibin Yan, Hui Xu
2023ISCASDesign of Low-Cost Approximate CMOS Full Adders.Aibin Yan, Shaojie Wei, Zhixing Li, Jie Cui, Zhengfeng Huang, Patrick Girard, Xiaoqing Wen
2022DATESCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments.Aibin Yan, Zhixing Li, Shiwei Huang, Zijie Zhai, Xiangyu Cheng, Jie Cui, Tianming Ni, Xiaoqing Wen, Patrick Girard
2022VLSIDPower and Energy Safe Real-Time Multi-Core Task Scheduling.Kalyan Baital, Amlan Chakrabarti, Biswadeep Chatterjee, Stefan Holst, Xiaoqing Wen
2022VTSA Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications.Aibin Yan, Kuikui Qian, Jie Cui, Ningning Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard
2021DATEReliability-Driven Neuromorphic Computing Systems Design.Qi Xu, Junpeng Wang, Hao Geng, Song Chen, Xiaoqing Wen
2021ISCASTPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation.Aibin Yan, Liang Ding, Chuanbo Shan, Haoran Cai, Xiaofeng Chen, Zhanjun Wei, Zhengfeng Huang, Xiaoqing Wen
2021ISPAA Blockchain-based Verified Locating Scheme for IoT Devices.Zhenyu Guan, Xiaoqing Wen, Dawei Li, Mai Xu, Haihua Li
2020DACHITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications.Aibin Yan, Xiangfeng Feng, Xiaohu Zhao, Hang Zhou, Jie Cui, Zuobin Ying, Patrick Girard, Xiaoqing Wen
2020ISCASDual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications.Aibin Yan, Zhelong Xu, Jie Cui, Zuobin Ying, Zhengfeng Huang, Huaguo Liang, Patrick Girard, Xiaoqing Wen
2020ITCLogic Fault Diagnosis of Hidden Delay Defects.Stefan Holst, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, Xiaoqing Wen
2019DATESingle-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications.Aibin Yan, Yuanjie Hu, Jie Song, Xiaoqing Wen
2019ETSSTAHL: A Novel Scan-Test-Aware Hardened Latch Design.Ruijun Ma, Stefan Holst, Xiaoqing Wen, Aibin Yan, Hui Xu
2019ITCVariation-Aware Small Delay Fault Diagnosis on Compressed Test Responses.Stefan Holst, Eric Schneider, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich
2019PRDCTargeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test.Stefan Holst, Shiling Shi, Xiaoqing Wen
2018ETSThe impact of production defects on the soft-error tolerance of hardened latches.Stefan Holst, Ruijun Ma, Xiaoqing Wen
2017ITCAnalysis and mitigation or IR-Drop induced scan shift-errors.Stefan Holst, Eric Schneider, Koshi Kawagoe, Michael A. Kochte, Kohei Miyase, Hans-Joachim Wunderlich, Seiji Kajihara, Xiaoqing Wen
2016ETSSAT-based post-processing for regional capture power reduction in at-speed scan test generation.Stephan Eggersgl, Kohei Miyase, Xiaoqing Wen
2015DATEGPU-accelerated small delay fault simulation.Eric Schneider, Stefan Holst, Michael A. Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich
2015ETSIdentification of high power consuming areas with gate type and logic level information.Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara
2015ETSA soft-error tolerant TCAM using partial don't-care keys.Infall Syafalni, Tsutomu Sasao, Xiaoqing Wen, Stefan Holst, Kohei Miyase
2014ICCADData-parallel simulation for fast and accurate timing validation of CMOS circuits.Eric Schneider, Stefan Holst, Xiaoqing Wen, Hans-Joachim Wunderlich
2013VLSIDOn Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression.Kazunari Enokimoto, Xiaoqing Wen, Kohei Miyase, Jiun-Lang Huang, Seiji Kajihara, Laung-Terng Wang
2012ETSPower-aware testing: The next stage.Xiaoqing Wen
2012ITCOn pinpoint capture power management in at-speed scan test generation.Xiaoqing Wen, Y. Nishida, Kohei Miyase, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor, Laung-Terng Wang
2012VTSA novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits.Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara
2011DATETransition-Time-Relation based capture-safety checking for at-speed scan test generation.Kohei Miyase, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara
2011ISLPEDSAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich
2011ITCClock-gating-aware low launch WSA test pattern generation for at-speed scan testing.Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen
2011ITCA novel scan segmentation design method for avoiding shift timing failure in scan testing.Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang
2011VTSPower-aware test generation with guaranteed launch safety for at-speed scan testing.Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor
2011VTSSpecial session 5B: Panel How much toggle activity should we be testing with?Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg
2010DDECSAnalysis of power consumption and transition fault coverage for LOS and LOC testing schemes.Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen
2010ETSOn estimation of NBTI-Induced delay degradation.Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura
2010ITCIs test power reduction through X-filling good enough?Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed
2009ICCADA novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara
2009PRDCA GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing.Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara
2008DATEPower-Aware Testing and Test Strategies for Low Power Devices.Dimitris Gizopoulos, Kaushik Roy, Patrick Girard, Nicola Nicolici, Xiaoqing Wen
2008DATETest Strategies for Low Power Devices.C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen
2008DDECSDiagnosis of Realistic Defects Based on the X-Fault Model.Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen
2008ETSA Capture-Safe Test Generation Scheme for At-Speed Scan Testing.Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja
2008ICCADEffective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification.Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara
2008ITCTurbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
2008ITCReducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing.Meng-Fan Wu, Jiun-Lang Huang, Xiaoqing Wen, Kohei Miyase
2007DACCritical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja
2007ETSEmbedded Tutorial on Low Power Test.Nicola Nicolici, Xiaoqing Wen
2007ICCADEstimation of delay test quality and its application to test generation.Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
2007ITCA novel scheme to reduce power supply noise for high-quality at-speed scan testing.Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang
2006ASPDACA dynamic test compaction procedure for high-quality path delay testing.Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2006ICCDHighly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja
2006ITCA Novel and Practical Control Scheme for Inter-Clock At-Speed Testing.Hiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu
2006ITCA Framework of High-quality Transition Fault ATPG for Scan Circuits.Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2006VTSA New ATPG Method for Efficient Capture Power Reduction During Scan Testing.Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita
2005ASPDACTest compression for scan circuits using scan polarity adjustment and pinpoint test relaxation.Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty
2005DACPath delay test compaction with process variation tolerance.Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato
2005DATEAt-Speed Logic BIST for IP Cores.B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu
2005ICCDAt-Speed Logic BIST Architecture for Multi-Clock Designs.Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo
2005ITCUltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction.Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang
2005ITCLow-capture-power test generation for scan-based at-speed testing.Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2005PRDCCompression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen
2005VTSOn Low-Capture-Power Test Generation for Scan Testing.Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2004ICCADOn per-test fault diagnosis using the X-fault model.Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita
2004ITCVirtualScan: A New Compressed Scan Technology for Test Cost Reduction.Laung-Terng Wang, Khader S. Abdel-Hafez, Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, Fei-Sheng Hsu, Shyh-Horng Lin, Sen-Wei Tsai
1996ICCADA new method towards achieving global optimality in technology mapping.Xiaoqing Wen, Kewal K. Saluja
1992ITCTestable Designs of Sequential Circuits Under Highly Observable Condition.Xiaoqing Wen, Kozo Kinoshita
1990ITCA testable design of logic circuits under highly observable condition.Xiaoqing Wen, Kozo Kinoshita