| 2010 | A 65nm embedded low power SRAM compiler. | Sheng Wu, Xiang Zheng, Zhiqiang Gao, Xiangqing He |
| 2010 | Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. | Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen |
| 2010 | A low power low voltage mixer for 2.4GHz applications in CMOS-90nm technology. | Alberto Villegas, Diego Vzquez, Adoracin Rueda |
| 2010 | Constraint-based test pattern generation at the Register-Transfer Level. | Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko |
| 2010 | Characterization of randomness sources in ring oscillator-based true random number generators in FPGAs. | Boyan Valtchanov, Viktor Fischer, Alain Aubert, Florent Bernard |
| 2010 | A fault-tolerant and congestion-aware routing algorithm for Networks-on-Chip. | Mojtaba Valinataj, Siamak Mohammadi, Juha Plosila, Pasi Liljeberg |
| 2010 | Versatile sub-bandgap reference IP core. | Toms Urban, Ondrej Subrt, Pravoslav Martnek |
| 2010 | A mixer-filter combination of a direct conversion receiver for DVB-H applications in 65nm CMOS. | Heimo Uhrmann, Lukas Drrer, Franz Kuttner, Kurt Schweiger, Horst Zimmermann |
| 2010 | Automated simulation-based verification of power requirements for Systems-on-Chips. | Christoph Trummer, Christoph M. Kirchsteiger, Christian Steger, Reinhold Weiss, Markus Pistauer, Damian Dalton |
| 2010 | Modeling temperature distribution in Networks-on-Chip using RC-circuits. | Andreas Tockhorn, Claas Cornelius, Hagen Smrow, Dirk Timmermann |
| 2010 | Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs. | Martin Straka, Jan Kastil, Zdenek Kotsek |
| 2010 | On the mitigation of SET broadening effects in integrated circuits. | Luca Sterpone, Niccol Battezzati |
| 2010 | Window optimization of reversible and quantum circuits. | Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler |
| 2010 | Noise determination of a current conveyor in an inverting voltage amplifier configuration. | Stylianos Siskos |
| 2010 | On analysis of fabricated polymorphic circuits. | Vclav Simek, Richard Ruzicka, Luks Sekanina |
| 2010 | Evolutionary circuit design: Tutorial. | Luks Sekanina |
| 2010 | Highly linear down-conversion mixer in 65nm CMOS for a high supply voltage of 2.5V. | Kurt Schweiger, Horst Zimmermann |
| 2010 | Software-based self-repair of statically scheduled superscalar data paths. | Mario Schlzel |
| 2010 | A hardware accelerated framework for the generation of design validation programs for SMT processors. | Danilo Ravotto, Ernesto Snchez, Matteo Sonza Reorda |
| 2010 | Developing reconfigurable FIFOs to optimize power/performance of Voltage/Frequency Island-based networks-on-chip. | Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen |
| 2010 | Simulation-based sensitivity and worst-case analyses of automotive electronics. | Monica Rafaila, Christian Decker, Christoph Grimm, Georg Pelz |
| 2010 | Memory optimizations for packet classification algorithms in FPGA. | Viktor Pus, Juraj Blaho, Jan Korenek |
| 2010 | Synthesis of asynchronous monitors for critical electronic systems. | Alexandre Porcher, Katell Morin-Allory, Laurent Fesquet |
| 2010 | SystemC-AMS SDF model synthesis for exploration of heterogeneous architectures. | Andreas Popp, Andreas Herrholz, Kim Grttner, Yannick Le Moullec, Peter Koch, Wolfgang Nebel |
| 2010 | A synthesis method to propagate false path information from RTL to gate level. | Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara |