| 2014 | Reducing embedded software radiation-induced failures through cache memories. | Thiago Santini, Paolo Rech, Gabriel L. Nazar, Luigi Carro, Flvio Rech Wagner |
| 2014 | Reconfigurable high performance architectures: How much are they ready for safety-critical applications? | Davide Sabena, Luca Sterpone, Mario Schlzel, Tobias Koal, Heinrich Theodor Vierhaus, S. Wong, Robrt Glein, Florian Rittner, C. Stender, Mario Porrmann, Jens Hagemeyer |
| 2014 | Two soft-error mitigation techniques for functional units of DSP processors. | Alireza Rohani, Hans G. Kerkhoff |
| 2014 | Post-bond test of Through-Silicon Vias with open defects. | Rosa Rodrguez-Montas, Daniel Arum, Joan Figueras |
| 2014 | Major eras of Design for Test. | Walden C. Rhines |
| 2014 | Analysis of cell-aware test pattern effectiveness - A case study using a 32-bit automotive microcontroller. | Athul Prabhu, Vlado Vorisek, Helmut Lang, Thomas Schumann |
| 2014 | Property-checking based LBIST for improved diagnosability. | Sarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao |
| 2014 | A distance-based test cube merging procedure for compatible and incompatible test cubes. | Irith Pomeranz |
| 2014 | Detection conditions for errors in self-adaptive better-than-worst-case designs. | Ilia Polian, Jie Jiang, Adit D. Singh |
| 2014 | INL systematic reduced-test technique for Pipeline ADCs. | Eduardo J. Peralas, Antonio Jose Gins, Adoracin Rueda |
| 2014 | A new efficiency criterion for security oriented error correcting codes. | Yaara Neumeier, Osnat Keren |
| 2014 | Interleaved scrambling technique: A novel low-power security layer for cache memories. | Madalin Neagu, Liviu Miclea, Salvador Manich |
| 2014 | An off-line MDSI interconnect BIST incorporated in BS 1149.1. | Marzieh Mohammadi, Somayeh Sadeghi Kohan, Nasser Masoumi, Zainalabedin Navabi |
| 2014 | Logic simulation and fault collapsing with shared structurally synthesized bdds. | Dmitri Mironov, Raimund Ubar, Jaan Raik |
| 2014 | Towards a general purpose mixed-signal instrumentation layer in the die stack of a 3D-SIC. | Shudong Lin, Gordon W. Roberts |
| 2014 | Using dynamic shift to reduce test data volume in high-compression designs. | Xijiang Lin, Mark Kassab, Janusz Rajski |
| 2014 | Built-in self-calibration of CMOS-compatible thermopile sensor with on-chip electrical stimulus. | Jia Li, Zhuolei Huang, Weibing Wang |
| 2014 | Output-bit selection with X-avoidance using multiple counters for test-response compaction. | Wei-Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong-Yu Hsieh |
| 2014 | GPU-based timing-aware test generation for small delay defects. | Kuan-Yu Liao, Po-Juei Chen, Ang-Feng Lin, James Chien-Mo Li, Michael S. Hsiao, Laung-Terng Wang |
| 2014 | Site dependencies in a multisite testing environment. | Thomas Lehner, Andreas Kuhr, Michael G. Wahl, Rainer Brck |
| 2014 | Improving polynomial datapath debugging with HEDs. | Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi |
| 2014 | Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs. | Fernanda Lima Kastensmidt, Jorge L. Tonfat, Thiago Hanna Both, Paolo Rech, Gilson I. Wirth, Ricardo Reis, Florent Bruguier, Pascal Benoit, Lionel Torres, Christopher Frost |
| 2014 | Homogeneous many-core processor system test distribution and execution mechanism. | Arezoo Kamran, Zainalabedin Navabi |
| 2014 | On the impact of process variability and aging on the reliability of emerging memories (Embedded tutorial). | Marco Indaco, Paolo Prinetto, Elena I. Vatajelu |
| 2014 | On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs. | Shi-Yu Huang, Zeng-Fu Zeng, Kun-Han Tsai, Wu-Tung Cheng |