| 2004 | An efficient scan tree design for test time reduction. | Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard |
| 2004 | Relating entropy theory to test data compression. | Kedarnath J. Balakrishnan, Nur A. Touba |
| 2004 | Signal integrity verification using high speed monitors. | Victor Avendao, Vctor H. Champac, Joan Figueras |
| 2003 | Enhanced P1500 compliant wrapper suitable for delay fault testing of embedded cores. | H. J. Vermaak, Hans G. Kerkhoff |
| 2003 | Parity-based output compaction for core-based SOCs [logic testing]. | Ozgur Sinanoglu, Alex Orailoglu |
| 2003 | RF ATE equipment benefit from advanced network analyzer technology. | Marten Seth |
| 2003 | On path selection for delay fault testing considering operating conditions [logic IC testing]. | Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
| 2003 | Yield analysis for repairable embedded memories. | Anuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen, Clemens Wouters, Harald P. E. Vranken, Krishnendu Chakrabarty |
| 2003 | Automating the device interface board modeling for virtual test. | Marco Rona, Gunter Krampl, Fritz Raczkowski |
| 2003 | An efficient approach to SoC wrapper design, TAM configuration and test scheduling. | Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre |
| 2003 | Modeling feedback bridging faults with non-zero resistance. | Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker |
| 2003 | Scan test strategy for asynchronous-synchronous interfaces [SoC testing]. | Octavian Petre, Hans G. Kerkhoff |
| 2003 | Characterization of the EME of integrated circuits with the help of the IEC standard 61967 [electromagnetic emission]. | Timm Ostermann, Bernd Deutschmann |
| 2003 | Debug architecture for system on chip taking full advantage of the test access port. | Erik Moerman, Sbastien Bocq, Johan Verfaillie |
| 2003 | On the selection of efficient arithmetic additive test pattern generators [logic test]. | Salvador Manich, L. Garca, Luz Balado, Emili Lupon, Josep Rius, Rosa Rodrguez-Montas, Joan Figueras |
| 2003 | Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits. | Eric Liau, Doris Schmitt-Landsiedel |
| 2003 | Automating test program generation in STIL - expectations and experiences using IEEE 1450 [standard test interface language]. | Helmut Lang, Bhuwnesh Pande, Heiko Ahrens |
| 2003 | Importance of dynamic faults for new SRAM technologies. | Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor |
| 2003 | Control-aware test architecture design for modular SOC testing. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2003 | Requirements for delay testing of look-up tables in SRAM-based FPGAs. | Patrick Girard, Olivier Hron, Serge Pravossoudovitch, Michel Renovell |
| 2003 | TPI for improving PR fault coverage of Boolean and three-state circuits. | M. J. Geuzebroek, Ad J. van de Goor |
| 2003 | A practical evaluation of I | Alessandra Fudoli, Alberto Ascagni, Davide Appello, Hans A. R. Manhaeve |
| 2003 | Code generation for functional validation of pipelined microprocessors. | Fulvio Corno, Giovanni Squillero, Matteo Sonza Reorda |
| 2003 | Defect-oriented dynamic fault models for embedded-SRAMs. | Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel |
| 2003 | Signal integrity loss in bus lines due to open shielding defects. | Victor Avendao, Vctor H. Champac, Joan Figueras |