| 2005 | Defective behaviours of resistive opens in interconnect lines. | Daniel Arum, Rosa Rodrguez-Montas, Joan Figueras |
| 2005 | A unified fault model and test generation procedure for interconnect opens and bridges. | Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker |
| 2004 | Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits. | Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh |
| 2004 | Delay chain based programmable jitter generator. | Tian Xia, Peilin Song, Keith A. Jenkins, Jien-Chung Lo |
| 2004 | Test planning and test resource optimization for droplet-based microfluidic systems. | Fei Su, Sule Ozev, Krishnendu Chakrabarty |
| 2004 | Pipelined test of SOC cores through test data transformations. | Ozgur Sinanoglu, Alex Orailoglu |
| 2004 | A new BIST scheme for 5GHz low noise amplifiers. | Jee-Youl Ryu, Bruce C. Kim, Iboun Taimiya Sylla |
| 2004 | Accurate tap-delay measurements using a di .erential oscillation technique. | Octavian Petre, H. G. Kerkho |
| 2004 | Software development for an open architecture test system. | Bruce R. Parnas, Ankan K. Pramanick, Mark Elston, Toshiaki Adachi |
| 2004 | Towards a BIST technique for noise figure evaluation. | Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin |
| 2004 | A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder. | Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gssel |
| 2004 | User-constrained test architecture design for modular SOC testing. | Ludovic A. Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre |
| 2004 | Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. | Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy |
| 2004 | All-pass SC biquad reconfiguration scheme for oscillation based analog BIST. | Uros Kac, Franc Novak |
| 2004 | At-speed on-chip diagnosis of board-level interconnect faults. | Artur Jutman |
| 2004 | A design methodology to realize delay testable controllers using state transition information. | Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara |
| 2004 | Tests for address decoder delay faults in RAMs due to inter-gate opens. | Ad J. van de Goor, Said Hamdioui, Zaid Al-Ars |
| 2004 | A compression-driven test access mechanism design approach. | Paul Theo Gonciari, Bashir M. Al-Hashimi |
| 2004 | Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. | Patrick Girard, Olivier Hron, Serge Pravossoudovitch, Michel Renovell |
| 2004 | Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage? | Franco Fummi, Cristina Marconcini, Graziano Pravadelli |
| 2004 | Automatic test pattern generation for resistive bridging faults. | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker |
| 2004 | Electrically-induced thermal stimuli for MEMS testing. | Norbert Dumas, Florence Azas, Laurent Latorre, Pascal Nouet |
| 2004 | Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan |
| 2004 | Mems built-in-self-test using MLS. | Achraf Dhayni, Salvador Mir, Libor Rufer |
| 2004 | Delay fault testing and silicon debug using scan chains. | Ramyanshu Datta, Antony Sebastine, Jacob A. Abraham |