| 2005 | Multiple errors produced by single upsets in FPGA configuration memory: a possible solution. | Matteo Sonza Reorda, Luca Sterpone, Massimo Violante |
| 2005 | A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points. | Arijit Raychowdhury, Swaroop Ghosh, Swarup Bhunia, Debjyoti Ghosh, Kaushik Roy |
| 2005 | DOT: new deterministic defect-oriented ATPG tool. | Jaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold A. Pleskacz |
| 2005 | Using dummy bridging faults to define a reduced set of target faults. | Irith Pomeranz, Sudhakar M. Reddy |
| 2005 | Low power embedded DRAMs with high quality error correcting capabilities. | Philipp hler, Sybille Hellebrand |
| 2005 | Convolutional compaction-driven diagnosis of scan failures. | Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer, Chen Wang |
| 2005 | Fault collapsing for flash memory disturb faults. | Mohammad Gh. Mohammad, Laila Terkawi |
| 2005 | Test for low cost CMOS image sensors. | Peter Maxwell |
| 2005 | Towards on-line testing of MEMS using electro-thermal excitation. | Frdrick Mailly, Florence Azas, Norbert Dumas, Laurent Latorre, Pascal Nouet |
| 2005 | Logic circuit testing for transient faults. | Smita Krishnaswamy, Igor L. Markov, John P. Hayes |
| 2005 | Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels. | Adam B. Kinsman, Nicola Nicolici |
| 2005 | Testing of MEMS-based microsystems. | Hans G. Kerkhoff |
| 2005 | Bias Superposition - An On-Line Test Strategy for a MEMS Based Conductivity Sensor. | Carl Jeffrey, Zhou Xu, Andrew Richardson |
| 2005 | Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation. | Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara |
| 2005 | Test scheduling for modular SOCs in an abort-on-fail environment. | Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen |
| 2005 | Test control for secure scan designs. | David Hly, Frdric Bancel, Marie-Lise Flottes, Bruno Rouzeyre |
| 2005 | The anatomy of nanometer timing failures. | Chuck Hawkins, Jaume Segura |
| 2005 | Coverage of formal properties based on a high-level fault model and functional ATPG. | Franco Fummi, Graziano Pravadelli, Franco Toto |
| 2005 | Stuck-open fault diagnosis with stuck-at model. | Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud |
| 2005 | Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. | Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan |
| 2005 | Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities. | Achraf Dhayni, Salvador Mir, Libor Rufer |
| 2005 | A programmable time measurement architecture for embedded memory characterization. | Matthew Collins, Bashir M. Al-Hashimi, J. Neil Ross |
| 2005 | Testing of resistive opens in CMOS latches and flip-flops. | Vctor H. Champac, Antonio Zenteno, Jos L. Garcia |
| 2005 | Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs. | Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda |
| 2005 | Automatic March tests generation for static and dynamic faults in SRAMs. | Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto |