| 2003 | Process-variability aware delay fault testing of ΔV | Daniel Arum-Delgado, Rosa Rodrguez-Montas, Jos Pineda de Gyvez, Guido Gronthoud |
| 2002 | Combining deterministic logic BIST with test point insertion. | Harald P. E. Vranken, Florian Meister, Hans-Joachim Wunderlich |
| 2002 | Silicon technology advances and implications on test. | Gregory S. Spirakis |
| 2002 | Dynamic test data transformations for average and peak power reductions. | Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu |
| 2002 | On selecting testable paths in scan designs. | Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara |
| 2002 | RESPIN++ - deterministic embedded test. | Lars Schfer, Rainer Dorsch, Hans-Joachim Wunderlich |
| 2002 | Modeling gate oxide short defects in CMOS minimum transistors. | Michel Renovell, Jean Marc Gallire, Florence Azas, Yves Bertrand |
| 2002 | System level testing of virtual switch (re-)configuration over IP. | Tiziana Margaria, Oliver Niese, Bernhard Steffen, Andrei Erochok |
| 2002 | A real world application used to implement a true IDDQ based test strategy (facts and figures). | Hans A. R. Manhaeve, Joseph S. Vaccaro, Loren Benecke, David Prystasz |
| 2002 | Novel ATPG algorithms for transition faults. | Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran |
| 2002 | Power constrained preemptive TAM scheduling. | Erik Larsson, Hideo Fujiwara |
| 2002 | Dependable testing of compactor MISR: an imperceptible problem? | Andrzej Hlawiczka, Michal Kopec |
| 2002 | Data invalidation analysis for scan-based debug on multiple-clock system chips. | Sandeep Kumar Goel, Bart Vermeulen |
| 2002 | A novel test time reduction algorithm for test architecture design for core-based system chips. | Sandeep Kumar Goel, Erik Jan Marinissen |
| 2002 | Investigations for minimum invasion digital only built-in "ramp" based test techniques for charge pump PLL's. | Martin John Burbidge, Frdric Poullet, Jim Tijou, Andrew M. D. Richardson |
| 2002 | Simulating realistic bridging and crosstalk faults in an industrial setting. | Jonathan Bradford, Hartmut Delong, Ilia Polian, Bernd Becker |
| 2002 | A high accuracy triangle-wave signal generator for on-chip ADC testing. | Serge Bernard, Florence Azas, Yves Bertrand, Michel Renovell |
| 2002 | ATPG for timing-induced functional errors on trigger events in hardware-software systems. | Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris |
| 2001 | An implementation for test-time reduction in VLIW transport-triggered architectures. | V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff |
| 2001 | A fault model for function and delay testing. | Joonhwan Yi, John P. Hayes |
| 2001 | The use of equivalent fault analysis to improve static D.C. fault diagnosis - a potentiometric DAC case study. | Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee |
| 2001 | Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations. | Herman J. Vermaak, Hans G. Kerkhoff |
| 2001 | On-chip signal level evaluation for mixed-signal ICs using digital window comparators. | Daniela De Venuto, M. J. Ohletzo, Bruno Ricc |
| 2001 | RTL design validation, DFT and test pattern generation for high defects coverage. | Marcelino B. Santos, Fernando M. Gonalves, Isabel C. Teixeira, Joo Paulo Teixeira |
| 2001 | A VHDL-based virtual test concept for pre-silicon test-program debug. | Marco Rona, Gunter Krampl |