| 2001 | Analyzing bridging faults impact on EEPROM cell array. | Jean-Michel Portal, Annie Prez |
| 2001 | Automated regression testing of CTI-systems. | Oliver Niese, Tiziana Margaria, Andreas Hagerer, Bernhard Steffen, Georg Brune, Werner Goerigk, Hans-Dieter Ide |
| 2001 | A packet switching communication-based test access mechanism for system chips. | Mohsen Nahvi, Andr Ivanov |
| 2001 | Internal feedback bridging faults in combinational CMOS circuits: analysis and testing. | Yukiya Miura, Shuichi Seno |
| 2001 | System level diagnosis - a comparison of two alternative approaches. | Maisaa Khalil, Chantal Robach |
| 2001 | System-level DFT for consumer products. | D. C. L. (Erik) van Geest, Frans G. M. de Jong |
| 2001 | Reducing analogue fault-simulation time by using high-level modelling in dotss for an industrial design. | Liquan Fang, Guido Gronthoud, Hans G. Kerkhoff |
| 2001 | Using at-speed BIST to test LVDS serializer/deserializer function. | Magnus Eckersand, Fredrik Franzon, Ken Filliter |
| 2001 | Reusing scan chains for test pattern decompression. | Rainer Dorsch, Hans-Joachim Wunderlich |
| 2001 | On hardware generation of random single input change test sequences. | Ren David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel |
| 2001 | Demodulation based testing of off-chip driver performance. | Wilfried Daehn |
| 2000 | Compressed bit fail maps for memory fail pattern classification. | Jrg E. Vollrath, Ulf Lederer, Thomas Hladschik |
| 2000 | Delay fault testing: choosing between random SIC and random MIC test sequences. | Arnaud Virazel, Ren David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch |
| 2000 | Static and dynamic on-chip test response evaluation using a two-mode comparator. | Daniela De Venuto, Michael J. Ohletz, G. Matarrese |
| 2000 | Bridging the testing speed gap: design for delay testability. | Han Speek, Hans G. Kerkhoff, Manoj Sachdev, Mansour Shashaani |
| 2000 | RTL-based functional test generation for high defects coverage in digital SOCs. | Marcelino B. Santos, Fernando M. Gonalves, Isabel C. Teixeira, Joo Paulo Teixeira |
| 2000 | Defect detection from visual abnormalities in manufacturing process using I | Masaru Sanada |
| 2000 | Analyzing the test generation problem for an application-oriented test of FPGAs. | Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian |
| 2000 | On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | How to avoid random walks in hierarchical test path identification. | Yiorgos Makris, Jamison Collins, Alex Orailoglu |
| 2000 | System-level test bench generation in a co-design framework. | Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno |
| 2000 | Test challenges in nanometer technologies. | Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche |
| 2000 | Comparison of defect detection capabilities of current-based and voltage-based test methods. | Bram Kruseman |
| 2000 | Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path. | Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof |
| 2000 | LEAP: An accurate defect-free I | Antoni Ferr, Joan Figueras |