| 2000 | A parameterizable fault simulator for bridging faults. | Piet Engelke, Bernd Becker, Martin Keim |
| 2000 | CA-CSTP: a new BIST architecture for sequential circuits. | Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante |
| 2000 | Current testing procedure for deep submicron devices. | Anton Chichkov, Dirk Merlier, Peter Cox |
| 2000 | A system level boundary scan controller board for VME applications [to CERN experiments]. | Nuno Cardoso, Carlos Beltrn Almeida, Jos Carlos da Silva |
| 2000 | Microprocessor cores. | Andrew Burdass, Gary Campbell, Richard Grisenthwaite, David Gwilt, Peter Harrod, Richard York |
| 2000 | Combining symbolic and genetic techniques for efficient sequential circuit test generation. | Marco Boschini, Xiaoming Yu, Franco Fummi, Elizabeth M. Rudnick |
| 2000 | An effective distributed BIST architecture for RAMs. | Monica Lobetti Bodoni, Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto |
| 2000 | Hierarchical defect-oriented fault simulation for digital circuits. | Mykola Blyzniuk, T. Cibkov, Elena Gramatov, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar |
| 2000 | A method for trading off test time, area and fault coverage in datapath BIST synthesis. | David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre |
| 2000 | Low cost concurrent test implementation for linear digital systems. | Ismet Bayraktaroglu, Alex Orailoglu |
| 2000 | Towards an ADC BIST scheme using the histogram test technique. | Florence Azas, Serge Bernard, Y. Betrand, Michel Renovell |
| 1999 | A new approach for the nonlinearity test of ADCs/DACs and its application for BIST. | Fang Xu |
| 1999 | Debug facilities in the TriMedia CPU64 architecture. | Harald P. E. Vranken |
| 1999 | On the fault-injection-caused increase of the DAE-index in analogue fault simulation. | Bernd Straube, Kurt Reinschke, Wolfgang Vermeiren, Klaus Rbenack, Bert Mller, Christoph Clau |
| 1999 | On random pattern testability of cryptographic VLSI cores. | Andreas Schubert, Walter Anheier |
| 1999 | Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. | Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian |
| 1999 | Functional and structural testing of switched-current circuits. | Michel Renovell, Florence Azas, J.-C. Bodin, Yves Bertrand |
| 1999 | High-level path activation technique to speed up sequential circuit test generation. | Jaan Raik, Raimund Ubar |
| 1999 | On avoiding undetectable faults during test generation. | Irith Pomeranz, Sudhakar M. Reddy |
| 1999 | Experimental results on BIC sensors for transient current testing. | Rodrigo Picos, Miquel Roca, Eugeni Isern, Jaume Segura, Eugenio Garca-Moreno |
| 1999 | Cost effective testing of systems on silicon: areas for optimization. | Peter Muhmenthaler |
| 1999 | Extending fault-based testing to microelectromechanical systems. | Salvador Mir, Benot Charlot, Bernard Courtois |
| 1999 | The role of test protocols in testing embedded-core-based system ICs. | Erik Jan Marinissen, Maurice Lousberg |
| 1999 | Low power BIST by filtering non-detecting vectors. | Salvador Manich, A. Gabarr, M. Lopez, Joan Figueras, Patrick Girard, Los Guiller, Christian Landrault, Serge Pravossoudovitch, Joo Paulo Teixeira, Marcelino B. Santos |
| 1999 | Application of supply current testing to analogue circuits, towards a structural analogue test methodology. | Hans A. R. Manhaeve, Johan Verfaillie, B. Straka, J. P. Cornil |