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ACM Int'l Symposium on Field Programmable Gate Arrays

FPGA

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

1,710

1992–2026

Papers per year

199294 peak2026

FPGA papers

1,710 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2012A coarse-grained stream architecture for cryo-electron microscopy images 3D reconstruction.Wendi Wang, Bo Duan, Wen Tang, Chunming Zhang, Guangming Tan, Peiheng Zhang, Ninghui Sun
2012A field programmable array core for image processing (abstract only).Declan Walsh, Piotr Dudek
2012Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power.Warren Wai-Kit Shum, Jason Helge Anderson
2012Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only).Andr Seffrin, Sorin A. Huss
2012Adaptive FPGA-based robotics state machine architecture derived with genetic algorithms (abstract only).Jesus Savage, Rodrigo Savage, Marco Morales-Aguirre, ngel Fernando Kuri Morales
2012Efficient in-system RTL verification and debugging using FPGAs (abstract only).Proshanta Saha, Chuck Haymes, Ralph Bellofatto, Bernard Brezzo, Mohit Kapur, Sameh W. Asaad
2012The VTR project: architecture and CAD for FPGAs from verilog to routing.Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson
2012Reliability of a softcore processor in a commercial SRAM-based FPGA.Nathaniel H. Rollins, Michael J. Wirthlin
2012Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only).Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani
2012Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones.Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne
2012CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs.Michael Papamichael, James C. Hoe
2012Dataflow-driven execution control in a coarse-grained reconfigurable array (abstract only).Robin Panda, Scott Hauck
2012Reducing the cost of floating-point mantissa alignment and normalization in FPGAs.Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk
2012FCache: a system for cache coherent processing on FPGAs.Vincent Mirian, Paul Chow
2012Limit study of energy & delay benefits of component-specific routing.Nikil Mehta, Raphael Rubin, Andr DeHon
2012Power-aware FPGA technology mapping for programmable-VT architectures (abstract only).Wei Ting Loke, Yajun Ha
2012Accelerator compiler for the VENICE vector processor.Zhiduo Liu, Aaron Severance, Satnam Singh, Guy G. F. Lemieux
2012Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation.Haoran Li, Youn Sung Park, Zhengya Zhang
2012Operation scheduling and architecture co-synthesis for energy-efficient dataflow computations on FPGAs (abstract only).Colin Yu Lin, Ngai Wong, Hayden Kwok-Hay So
2012Compiling high throughput network processors.Maysam Lavasani, Larry Dennison, Derek Chiou
2012OCTAVO: an FPGA-centric processor family.Charles Eric LaForest, John Gregory Steffan
2012Multi-ported memories for FPGAs via XOR.Charles Eric LaForest, Ming G. Liu, Emma Rae Rapati, J. Gregory Steffan
2012VirtualRC: a virtual FPGA platform for applications and tools portability.Robert Kirchgessner, Greg Stitt, Alan D. George, Herman Lam
2012A real-time stereo vision system using a tree-structured dynamic programming on FPGA.Minxi Jin, Tsutomu Maruyama
2012Thermal-aware logic block placement for 3D FPGAs considering lateral heat dissipation (abstract only).Juinn-Dar Huang, Ya-Shih Huang, Mi-Yu Hsu, Han-Yuan Chang
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