| 2006 | Simulative analysis of dynamic scheduling heuristics for reconfigurable computing of parallel applications. | Rajagopal Subramaniyan, Ian A. Troxel, Alan D. George, Melissa C. Smith |
| 2006 | A reconfigurable architecture for hybrid CMOS/Nanodevice circuits. | Dmitri B. Strukov, Konstantin K. Likharev |
| 2006 | A novel methodology for designing high-performance and low-energy FPGA routing architecture. | Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis |
| 2006 | A generic lookup cache architecture for network processing applications. | Janardhan Singaraju, John A. Chandy |
| 2006 | A real-time implementation of Richardson-Lucy deconvolution. | Oliver Sims, James Irvine |
| 2006 | A Performance model for accelerating scientific applications on reconfigurable computers. | Ronald Scrofano, Viktor K. Prasanna |
| 2006 | The routability of multiprocessor network topologies in FPGAs. | Manuel Saldaa, Lesley Shannon, Paul Chow |
| 2006 | A programmable majority logic array using molecular scale electronics. | Garrett S. Rose, Mircea R. Stan |
| 2006 | A compact FPGA implementation of the hash function whirlpool. | Norbert Pramstaller, Christian Rechberger, Vincent Rijmen |
| 2006 | Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic. | Joshua Noseworthy, Miriam Leeser |
| 2006 | Testing embedded RAM modules in SRAM-based FPGAs. | Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali |
| 2006 | A reconfigurable architecture for network intrusion detection using principal component analysis. | David T. Nguyen, Gokhan Memik, Alok N. Choudhary |
| 2006 | Autonomous-repair cell for fault tolerant dynamic-reconfigurable devices. | Kentaro Nakahara, Shin'ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura |
| 2006 | A multilevel hierarchical interconnection structure for FPGA. | Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez |
| 2006 | Improvements to technology mapping for LUT-based FPGAs. | Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton |
| 2006 | High speed FIR filter implementation using add and shift method. | Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner |
| 2006 | Fast and accurate resource estimation of automatically generated custom DFT IP cores. | Peter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Pschel |
| 2006 | A reconfigurable hardware based embedded scheduler for buffered crossbar switches. | Lotfi Mhamdi, Christopher Kachris, Stamatis Vassiliadis |
| 2006 | FPGAs with multidimensional mesh topology. | Yohei Matsumoto, Hanpei Koike, Akira Masaki |
| 2006 | An iterative division algorithm for FPGAs. | Jianhua Liu, Michael Chang, Chung-Kuan Cheng |
| 2006 | Performance benefits of monolithically stacked 3D-FPGA. | Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong |
| 2006 | FPGA clock network architecture: flexibility vs. area and power. | Julien Lamoureux, Steven J. E. Wilton |
| 2006 | Measuring the gap between FPGAs and ASICs. | Ian Kuon, Jonathan Rose |
| 2006 | Effective clustering technique to optimize routability of outer cluster nets. | Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi |
| 2006 | Design, implementation, and verification of active cache emulator (ACE). | Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu |