| 2001 | A crosstalk-aware timing-driven router for FPGAs. | Steven J. E. Wilton |
| 2001 | Run-Time defect tolerance using JBits. | Prasanna Sundararajan, Steve Guccione |
| 2001 | Attacking the semantic gap between application programming languages and configurable hardware. | Greg Snider, Barry Shackleford, Richard J. Carter |
| 2001 | Interconnect pipelining in a throughput-intensive FPGA architecture. | Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska |
| 2001 | The case for registered routing switches in field programmable gate arrays. | Deshanand P. Singh, Stephen Dean Brown |
| 2001 | Mixing buffers and pass transistors in FPGA routing architectures. | Mike Sheng, Jonathan Rose |
| 2001 | A pipelined architecture for partitioned DWT based lossy image compression using FPGA's. | Jrg Ritter, Paul Molitor |
| 2001 | FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression. | Seetharaman Ramachandran, S. Srinivasan |
| 2001 | Runtime and quality tradeoffs in FPGA placement and routing. | Chandra Mulpuri, Scott Hauck |
| 2001 | Matching and searching analysis for parallel hardware implementation on FPGAs. | Pablo Moisset, Pedro C. Diniz, Joonseok Park |
| 2001 | Reprogrammable network packet processing on the field programmable port extender (FPX). | John W. Lockwood, Naji Naufel, Jonathan S. Turner, David E. Taylor |
| 2001 | An FPGA-based video compressor for H.263 compatible bit streams. | Gerhard Lienhart, Reinhard Mnner, Klaus-Henning Noffz, Ralf Lay |
| 2001 | Using sparse crossbars within LUT. | Guy G. Lemieux, David M. Lewis |
| 2001 | LRoute: a delay minimal router for hierarchical CPLDs. | K. K. Lee, D. F. Wong |
| 2001 | Is marriage in the cards for programmable logic, microprocessors and ASICs? | Sinan Kaptanoglu, John East, Tim Garverick, Scott Hauck, Tavana Tavana, Steven Trimberger, Ronnie Vasishta |
| 2001 | A memory coherence technique for online transient error recovery of FPGA configurations. | Wei-Je Huang, Edward J. McCluskey |
| 2001 | Detailed routing architectures for embedded programmable logic IP cores. | Peter Hallschmid, Steven J. E. Wilton |
| 2001 | Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. | Janette Frigo, Maya B. Gokhale, Dominique Lavenier |
| 2001 | Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware. | Mike Estlick, Miriam Leeser, James Theiler, John J. Szymanski |
| 2001 | Configuration compression for FPGA-based embedded systems. | Andreas Dandalis, Viktor K. Prasanna |
| 2001 | Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. | Pawel Chodowiec, Po Khuon, Kris Gaj |
| 2001 | Performance-driven mapping for CPLD architectures. | Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang |
| 2001 | Simultaneous logic decomposition with technology mapping in FPGA designs. | Gang Chen, Jason Cong |
| 2001 | The effect of reconfigurable units in superscalar processors. | Jorge E. Carrillo, Paul Chow |
| 2000 | A C compiler for a processor with a reconfigurable functional unit. | Zhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerjee |