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ACM Int'l Symposium on Field Programmable Gate Arrays

FPGA

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

1,710

1992–2026

Papers per year

199294 peak2026

FPGA papers

1,710 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
1999Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs.Yaska Sankar, Jonathan Rose
1999A Computational Intelligence Based Coarse-Grained Reconfigurable Element.C. Hart Poskar, Peter J. Czezowski, Robert D. McLeod
1999Design Issues in the Development of a JAVA-Processor for Small Embedded Applications.Hagen Ploog, Tino Rachui, Dirk Timmermann
1999Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures.S. R. Park, Wayne P. Burleson
1999The X-MatchLITE FPGA-Based Data Compressor.Jos Luis Nez, Claudia Feregrino, Stephen Bateman, Simon R. Jones
1999400-MHz Frequency Counter: A Case Study in Semi-Synchronous Design.Bernie New, Peter Alfke
1999High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA.Lirida A. B. Naviner, Jean-Luc Danger, C. Laurent
1999Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT.Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
1999Dynamically Programmable Cache Evaluation and Virtualization.Mouna Nakkar, David G. Bentlage, John Harding, David Schwartz, Paul D. Franzon, Thomas M. Conte
1999Why a CAD-Verified FPGA Makes Routing so Simple and Fast! A Result of Co-Designing FPGAs and CAD Algorithms.Takahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki
1999A FPGA-Based Hardware Implementation of Generalized Profile Search Using Online Arithmetic.Emeka Mosanya, Eduardo Sanchez
1999Practical Applications of Recursive VHDL Components in FPGA Synthesis.John McCluskey
1999High Speed Calculation of Cyclic Redundancy Codes.John McCluskey
1999A Method for Implementing Fractal Image Compression on Reconfigurable Architecture.Akihiro Matsuura, Hidehisa Nagano, Akira Nagoya
1999A Reconfigurable Arithmetic Array for Multimedia Application.Alan Marshall, Tony Stansfield, Igor Kostarnov, Jean Vuillemin, Brad L. Hutchings
1999Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density.Alexander Marquardt, Vaughn Betz, Jonathan Rose
1999Circuit Partitioning for Dynamically Reconfigurable FPGAs.Huiqun Liu, D. F. Wong
1999Don't Care Discovery for FPGA Configuration Compression.Zhiyuan Li, Scott Hauck
1999FPGA Based Computer Vision Camera.A. Lecerf, Franois Vachon, D. Ouellet, Miguel O. Arias-Estrada
1999Self-Checking Logic Design for LUT-Based FPGAs.Parag K. Lala, Alfred L. Burress
1999Efficient Support of Hardware Debugging Through FPGA Physical Design Partitioning.John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak
1999Partitioning Large Designs by Filling PFGA Devices with Hierarchy Blocks.Helena Krupnova, Gabriele Saucier
1999ATLANTIS - A Hybrid Approach Combining the Power of FPGA and RISC Processors Based on CompactPCI.Klaus Kornmesser, Torsten Kuberka, Andreas Kugel, Reinhard Mnner, Stephan Rhl, M. Sessler, Holger Singpiel
1999Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs.Peter Kollig, Bashir M. Al-Hashimi
1999Unified Access to Heterogeneous Module Generators.Andreas Koch
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