| 2002 | Implementation of a Successive Erasure BCH(16, 7, 6) Decoder and Performance Simulation by Rapid Prototyping. | Thomas Buerner |
| 2002 | Compiling Application-Specific Hardware. | Mihai Budiu, Seth Copen Goldstein |
| 2002 | Integration of Reconfigurable Hardware into System-Level Design. | Klaus Buchenrieder, Ulrich Nageldinger, Andreas Pyttel, Alexander Sedlmeier |
| 2002 | Multithreading for Logic-Centric Systems. | Gordon J. Brebner |
| 2002 | Challenges and Opportunities for FPGA Platforms. | Ivo Bolsens |
| 2002 | A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip. | Spyros Blionas, Kostas Masselos, Chrissavgi Dre, Christos Drosos, F. Z. Ieromnimon, T. Pagonis, Aristodemos Pneymatikakis, Anna Tatsaki, T. Trimis, A. Vontzalidis, Dimitris Metafas |
| 2002 | Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices. | Jean-Luc Beuchat, Arnaud Tisserand |
| 2002 | A Prolog-Based Hardware Development Environment. | Khaled Benkrid, Danny Crookes, Abdsamad Benkrid, Samir Belkacemi |
| 2002 | A Quantitative Understanding of the Performance of Reconfigurable Coprocessors. | Domingo Benitez |
| 2002 | A Library of Parameterized Floating-Point Modules and Their Use. | Pavle Belanovic, Miriam Leeser |
| 2002 | An Enhanced POLIS Framework for Fast Exploration and Implementation of I/O Subsystems on CSoC Platforms. | Massimo Baleani, Massimo Conti, Alberto Ferrari, Valerio Frascolla, Alberto L. Sangiovanni-Vincentelli |
| 2002 | An FPGA Co-processor for Real-Time Visual Tracking. | Miguel Arias-Estrada, Eduardo Rodrguez-Palacios |
| 2002 | Parallel FPGA Implementation of the Split and Merge Discrete Wavelet Transform. | Nazeeh Aranki, Alexander Moopenn, Raoul Tawel |
| 2002 | Threshold Element-Based Symmetric Function Generators and Their Functional Extension. | Kazuo Aoyama, Hiroshi Sawada |
| 2002 | Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing. | Abbes Amira, Ahmed Bouridane, Peter Milligan, Faycal Bensaali |
| 2001 | Arithmetic Operation Oriented Reconfigurable Chip: RHW. | Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara |
| 2001 | Bubble Partitioning for LUT-Based Sequential Circuits. | Frank Wolz, Reiner Kolla |
| 2001 | Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures. | Michael J. Wirthlin, Brian McMurtrey |
| 2001 | Synthesizing RTL Hardware from Java Byte Codes. | Michael J. Wirthlin, Brad L. Hutchings, Carl D. Worth |
| 2001 | FPGA Resource Reduction Through Truncated Multiplication. | Kent E. Wires, Michael J. Schulte, Don McCarley |
| 2001 | Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. | Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings |
| 2001 | Task-Parallel Programming of Reconfigurable Systems. | Markus Weinhardt, Wayne Luk |
| 2001 | Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware. | Nikolaus Vo, Brbel Mertsching |
| 2001 | A Digit-Serial Structure for Reconfigurable Multipliers. | Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk |
| 2001 | The MOLEN rho-mu-Coded Processor. | Stamatis Vassiliadis, Stephan Wong, Sorin Cotofana |