Skip to content

Field Programmable Logic and Applications

FPL

B

CORE rank

CORE rank (raw)

B

Fields of research

Computer Systems Engineering

Papers indexed

3,233

1994–2025

Papers per year

1994182 peak2025

FPL papers

3,233 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2008FPGAS in high energy physics experiments at CERN.L. Musa
2008Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration.Diego Pedro Morales, Antonio Garca, Alberto J. Palma, Miguel ngel Carvajal, Encarnacin Castillo, Luis F. Capitn-Vallvey
2008A scalable computing and memory architecture for variable block size motion estimation on Field-Programmable Gate Arrays.Theepan Moorthy, Andy Ye
2008Chosen-message SPA attacks against FPGA-based RSA hardware implementations.Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2008Power efficient DSP datapath configuration methodology for FPGA.Stephen McKeown, Roger F. Woods, John McAllister
2008An FPGA architecture for the Pagerank eigenvector problem.Samas McGettrick, Dermot Geraghty, Ciarn McElroy
2008GICS: Generic interconnection system.Tamas Malek, Toms Martnek, Jan Korenek
2008FPGA family composition and effects of specialized blocks.Pongstorn Maidee, Nagib Hakim, Kia Bazargan
2008A portable abstraction layer for hardware threads.Enno Lbbers, Marco Platzner
2008ATCA-based computation platform for data acquisition and triggering in particle physics experiments.Ming Liu, Johannes Lang, Shuo Yang, Tiago Perez, Wolfgang Kuehn, Hao Xu, Dapeng Jin, Qiang Wang, Lu Li, Zhen'An Liu, Zhonghai Lu, Axel Jantsch
2008Comparing throughput and power consumption in both sequential and reconfigurable processors.Kevin K. Liu, Charles B. Cameron, Antal A. Sarkady
2008Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework.Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung
2008An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects.Hanyu Liu, Xiaolei Chen, Yajun Ha
2008Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC.Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez
2008Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system.Brian Leung, Yan Pan, Christopher L. Schroeder, Seda Ogrenci Memik, Gokhan Memik, Mitra J. Z. Hartmann
2008Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA.Hoang Le, Weirong Jiang, Viktor K. Prasanna
2008Floating point datapath synthesis for FPGAs.Martin Langhammer
2008Hyperreconfigurable architectures.Sebastian Lange, Martin Middendorf
2008Low-latency high-bandwidth HW/SW communication in a virtual memory environment.Holger Lange, Andreas Koch
2008An analytical model describing the relationships between logic architecture and FPGA density.Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
2008Mapping and scheduling with task clustering for heterogeneous computing systems.Yuet Ming Lam, Jos Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong
2008Application-adaptive reconfiguration of memory address shuffler for FPGA-embedded instruction-set processor.Young-Su Kwon, Bontae Koo, Nak-Woong Eum
2008Digital hilbert transformers for FPGA-based phase-locked loops.Martin Kumm, M. Shahab Sanjari
2008A flexible and reliable embedded system for detector control in a high energy physics experiment.Tobias Krawutschke
2008Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching.George Kornaros, Wolfram Lautenschlaeger, Matthias Sund, Helen-Catherine Leligou
1,6761,700 of 3,233← PreviousNext →

Comparable venues

Other A*/A conferences filed under the same field of research.