| 2008 | Exploring FPGA network on chip implementations across various application and network loads. | Graham Schelle, Dirk Grunwald |
| 2008 | Seamless design flow for reconfigurable systems. | Andreas Schallenberg, Achim Rettberg, Wolfgang Nebel, Franz-Josef Rammig |
| 2008 | Operating system support for online partial dynamic reconfiguration management. | Marco D. Santambrogio, Vincenzo Rana, Donatella Sciuto |
| 2008 | Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. | Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano |
| 2008 | Bio-inspiration helps computers: A new machine. | Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert |
| 2008 | How fast is an FPGA in image processing? | Takashi Saegusa, Tsutomu Maruyama, Yoshiki Yamaguchi |
| 2008 | Teaching FPGA system design via a remote laboratory facility. | Yamuna Rajasekhar, William V. Kritikos, Andrew G. Schmidt, Ron Sass |
| 2008 | Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory. | Meikang Qiu, Jiande Wu, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean Sha |
| 2008 | CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures. | Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan, Susan J. Eggers |
| 2008 | Convergence analysis of run-time distributed optimization on adaptive systems using game theory. | Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres |
| 2008 | Network processors. | Thilo Pionteck, Roman Koch, Carsten Albrecht, Erik Maehle, Michael Meitinger, Rainer Ohlendorf, Thomas Wild, Andreas Herkersdorf |
| 2008 | On the design parameters of runtime reconfigurable systems. | Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle |
| 2008 | EMMA - A suggestion for an embedded multi-precision multiplier array for FPGAs. | Oliver A. Pfnder, Hans-Jrg Pfleiderer |
| 2008 | A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. | Roberto Perez-Andrade, Ren Cumplido, Claudia Feregrino-Uribe, Fernando Martin del Campo |
| 2008 | Cluster architecture based on low cost reconfigurable hardware. | Csar Pedraza, Emilio Castillo, Javier Castillo, Cristobal Camarero, Jos Luis Bosque, Jos Ignacio Martnez, Rafael Menndez de Llano |
| 2008 | Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. | Katarina Paulsson, Michael Hbner, Jrgen Becker |
| 2008 | Efficient FPGA mapping of Gilbert's algorithm for SVM training on large-scale classification problems. | Markos Papadonikolakis, Christos-Savvas Bouganis |
| 2008 | Polymorphic wavelet architectures using reconfigurable hardware. | Amit Pande, Joseph Zambreno |
| 2008 | A configurable and programmable motion estimation processor for the H.264 video codec. | Jos Luis Nez-Yez, Eddie Hung, Vassilios A. Chouliaras |
| 2008 | Power reduction techniques for Dynamically Reconfigurable Processor Arrays. | Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano |
| 2008 | Modeling recursion data structures for FPGA-based implementation. | Spyridon Ninos, Apostolos Dollas |
| 2008 | Direct sigma-delta modulated signal processing in FPGA. | Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng |
| 2008 | Decimal multiplier on FPGA using embedded binary multipliers. | Horcio C. Neto, Mrio P. Vstias |
| 2008 | Numerical function generators using bilinear interpolation. | Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler |
| 2008 | Interface and Reconfiguration Controller for a wireless MAC-oriented dynamically reconfigurable hardware co-processor. | Syed Waqar Nabi, Cade C. Wells, Wim Vanderbauwhede |